yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-10-21 00:08:22 +02:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Add PSTATE.BTYPE

Browse Source 
Place this in its own field within ENV, as that will
make it easier to reset from within TCG generated code.

With the change to pstate_read/write, exception entry
and return are automatically handled.

Backports commit f6e52eaac13b6947f4406c127e3090c898e439c9 from qemu
This commit is contained in:
Richard Henderson 2019-02-05 16:57:48 -05:00 committed by Lioncash
parent 6b4f7a28b5
commit a99119ce39
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
2 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
qemu/target/arm/cpu.h
View File

@ -225,6 +225,7 @@ typedef struct CPUARMState {
* semantics as for AArch32, as described in the comments on each field) * semantics as for AArch32, as described in the comments on each field)
* nRW (also known as M[4]) is kept, inverted, in env->aarch64 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
* DAIF (exception masks) are kept in env->daif * DAIF (exception masks) are kept in env->daif
* BTYPE is kept in env->btype
* all other bits are stored in their correct places in env->pstate * all other bits are stored in their correct places in env->pstate
*/ */
uint32_t pstate; uint32_t pstate;
@ -254,6 +255,7 @@ typedef struct CPUARMState {
uint32_t GE; /* cpsr[19:16] */ uint32_t GE; /* cpsr[19:16] */
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
uint32_t btype; /* BTI branch type. spsr[11:10]. */
uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */
uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t elr_el[4]; /* AArch64 exception link regs */
@ -1148,6 +1150,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_I (1U << 7) #define PSTATE_I (1U << 7)
#define PSTATE_A (1U << 8) #define PSTATE_A (1U << 8)
#define PSTATE_D (1U << 9) #define PSTATE_D (1U << 9)
#define PSTATE_BTYPE (3U << 10)
#define PSTATE_IL (1U << 20) #define PSTATE_IL (1U << 20)
#define PSTATE_SS (1U << 21) #define PSTATE_SS (1U << 21)
#define PSTATE_V (1U << 28) #define PSTATE_V (1U << 28)
@ -1156,7 +1159,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_N (1U << 31) #define PSTATE_N (1U << 31)
#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
/* Mode values for AArch64 */ /* Mode values for AArch64 */
#define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3h 13
#define PSTATE_MODE_EL3t 12 #define PSTATE_MODE_EL3t 12
@ -1188,7 +1191,7 @@ static inline uint32_t pstate_read(CPUARMState *env)
ZF = (env->ZF == 0); ZF = (env->ZF == 0);
return (env->NF & 0x80000000) | (ZF << 30) return (env->NF & 0x80000000) | (ZF << 30)
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
| env->pstate | env->daif; | env->pstate | env->daif | (env->btype << 10);
} }
static inline void pstate_write(CPUARMState *env, uint32_t val) static inline void pstate_write(CPUARMState *env, uint32_t val)
@ -1198,6 +1201,7 @@ static inline void pstate_write(CPUARMState *env, uint32_t val)
env->CF = (val >> 29) & 1; env->CF = (val >> 29) & 1;
env->VF = (val << 3) & 0x80000000; env->VF = (val << 3) & 0x80000000;
env->daif = val & PSTATE_DAIF; env->daif = val & PSTATE_DAIF;
env->btype = (val >> 10) & 3;
env->pstate = val & ~CACHED_PSTATE_BITS; env->pstate = val & ~CACHED_PSTATE_BITS;
} }

4
qemu/target/arm/translate-a64.c
View File

@ -177,7 +177,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
ns_status, ns_status,
el, el,
psr & PSTATE_SP ? 'h' : 't'); psr & PSTATE_SP ? 'h' : 't');
if (cpu_isar_feature(aa64_bti, cpu)) {
cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
}
if (!(flags & CPU_DUMP_FPU)) { if (!(flags & CPU_DUMP_FPU)) {
cpu_fprintf(f, "\n"); cpu_fprintf(f, "\n");
return; return;