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target-i386: Move warning code outside x86_cpu_filter_features()

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x86_cpu_filter_features() will be reused by code that shouldn't
print any warning. Move the warning code to a new
x86_cpu_report_filtered_features() function, and call it from
x86_cpu_realizefn().

Backports commit 8ca30e8673aff9bfcf8f969f8db4266b5f62e49c from qemu
This commit is contained in:
Eduardo Habkost 2018-02-26 09:40:08 -05:00 committed by Lioncash
parent 08bfa41e1b
commit aa98c8a93f
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 23 additions and 7 deletions
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30
qemu/target-i386/cpu.c
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@ -639,9 +639,9 @@ static const ExtSaveArea x86_ext_save_areas[] = {
static uint32_t xsave_area_size(uint64_t mask) static uint32_t xsave_area_size(uint64_t mask)
{ {
int i; int i;
uint64_t ret = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader); uint64_t ret = 0;
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i]; const ExtSaveArea *esa = &x86_ext_save_areas[i];
if ((mask >> i) & 1) { if ((mask >> i) & 1) {
ret = MAX(ret, esa->offset + esa->size); ret = MAX(ret, esa->offset + esa->size);
@ -2198,9 +2198,6 @@ static int x86_cpu_filter_features(X86CPU *cpu)
env->features[w] &= host_feat; env->features[w] &= host_feat;
cpu->filtered_features[w] = requested_features & ~env->features[w]; cpu->filtered_features[w] = requested_features & ~env->features[w];
if (cpu->filtered_features[w]) { if (cpu->filtered_features[w]) {
if (cpu->check_cpuid || cpu->enforce_cpuid) {
report_unavailable_features(w, cpu->filtered_features[w]);
}
rv = 1; rv = 1;
} }
} }
@ -2208,6 +2205,15 @@ static int x86_cpu_filter_features(X86CPU *cpu)
return rv; return rv;
} }
static void x86_cpu_report_filtered_features(X86CPU *cpu)
{
FeatureWord w;
for (w = 0; w < FEATURE_WORDS; w++) {
report_unavailable_features(w, cpu->filtered_features[w]);
}
}
static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
{ {
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
@ -3012,8 +3018,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
return; return;
} }
mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK); mask = 0;
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i]; const ExtSaveArea *esa = &x86_ext_save_areas[i];
if (env->features[esa->feature] & esa->bits) { if (env->features[esa->feature] & esa->bits) {
mask |= (1ULL << i); mask |= (1ULL << i);
@ -3098,6 +3104,16 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
env->cpuid_xlevel2 = env->cpuid_min_xlevel2; env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
} }
if (x86_cpu_filter_features(cpu) &&
(cpu->check_cpuid || cpu->enforce_cpuid)) {
x86_cpu_report_filtered_features(cpu);
if (cpu->enforce_cpuid) {
error_setg(&local_err,
"TCG doesn't support requested features");
goto out;
}
}
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
* CPUID[1].EDX. * CPUID[1].EDX.
*/ */