yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-10-19 00:28:26 +02:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: fix vill bit index in vtype register

Browse Source 
vill bit is at vtype[XLEN-1].

Backports fbcbafa2c1c33ae6630e7717f7f4141befb5b31a
This commit is contained in:
Frank Chang 2021-03-08 12:13:56 -05:00 committed by Lioncash
parent 61d69c8175
commit b1e52b7958
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
qemu/target/riscv/cpu.h
View File

@ -103,7 +103,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];