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tcg: Rename debug_insn_start to insn_start

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With an eye toward making it mandatory.

Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
This commit is contained in:
Lioncash 2018-02-11 12:31:22 -05:00
parent 77b03e0973
commit b3f9ff667b
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
23 changed files with 28 additions and 28 deletions
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2
qemu/aarch64.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_aarch64
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_aarch64
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64

2
qemu/aarch64eb.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_aarch64eb
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_aarch64eb
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64eb
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64eb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64eb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64eb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64eb
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64eb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64eb
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64eb

2
qemu/arm.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_arm
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_arm
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_arm
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_arm
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_arm
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_arm
#define tcg_gen_discard_i64 tcg_gen_discard_i64_arm
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
#define tcg_gen_insn_start tcg_gen_insn_start_arm
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_arm
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_arm

2
qemu/armeb.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_armeb
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_armeb
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_armeb
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_armeb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_armeb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_armeb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_armeb
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
#define tcg_gen_insn_start tcg_gen_insn_start_armeb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_armeb
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_armeb

2
qemu/header_gen.py
View File

@ -2725,7 +2725,6 @@ symbols = (
'tcg_gen_code_common',
'tcg_gen_code_search_pc',
'tcg_gen_concat_i32_i64',
'tcg_gen_debug_insn_start',
'tcg_gen_deposit_i32',
'tcg_gen_deposit_i64',
'tcg_gen_discard_i64',
@ -2753,6 +2752,7 @@ symbols = (
'tcg_gen_extrl_i64_i32',
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
'tcg_gen_insn_start',
'tcg_gen_ld16s_i64',
'tcg_gen_ld16u_i64',
'tcg_gen_ld32s_i64',

2
qemu/m68k.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_m68k
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_m68k
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_m68k
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_m68k
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_m68k
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_m68k
#define tcg_gen_discard_i64 tcg_gen_discard_i64_m68k
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
#define tcg_gen_insn_start tcg_gen_insn_start_m68k
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_m68k
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_m68k

2
qemu/mips.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_mips
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_mips
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
#define tcg_gen_insn_start tcg_gen_insn_start_mips
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips

2
qemu/mips64.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_mips64
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_mips64
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
#define tcg_gen_insn_start tcg_gen_insn_start_mips64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64

2
qemu/mips64el.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_mips64el
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_mips64el
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64el
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64el
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64el
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64el
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64el
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
#define tcg_gen_insn_start tcg_gen_insn_start_mips64el
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64el
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64el

2
qemu/mipsel.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_mipsel
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_mipsel
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mipsel
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mipsel
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mipsel
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mipsel
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mipsel
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
#define tcg_gen_insn_start tcg_gen_insn_start_mipsel
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mipsel
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mipsel

2
qemu/powerpc.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_powerpc
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_powerpc
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_powerpc
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_powerpc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_powerpc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_powerpc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_powerpc
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
#define tcg_gen_insn_start tcg_gen_insn_start_powerpc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_powerpc
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_powerpc

2
qemu/sparc.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_sparc
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_sparc
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
#define tcg_gen_insn_start tcg_gen_insn_start_sparc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc

2
qemu/sparc64.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_sparc64
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_sparc64
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc64
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
#define tcg_gen_insn_start tcg_gen_insn_start_sparc64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc64

2
qemu/target-arm/translate-a64.c
View File

@ -11285,7 +11285,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
//}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, dc->pc);
tcg_gen_insn_start(tcg_ctx, dc->pc);
}
if (dc->ss_active && !dc->pstate_ss) {

2
qemu/target-arm/translate.c
View File

@ -11482,7 +11482,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
// gen_io_start();
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, dc->pc);
tcg_gen_insn_start(tcg_ctx, dc->pc);
}
if (dc->ss_active && !dc->pstate_ss) {

2
qemu/target-i386/translate.c
View File

@ -5019,7 +5019,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, pc_start);
tcg_gen_insn_start(tcg_ctx, pc_start);
}
// Unicorn: trace this instruction on request

2
qemu/target-m68k/translate.c
View File

@ -3036,7 +3036,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
uint16_t insn;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, s->pc);
tcg_gen_insn_start(tcg_ctx, s->pc);
}
// Unicorn: end address tells us to stop emulation

2
qemu/target-mips/translate.c
View File

@ -18548,7 +18548,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, ctx->pc);
tcg_gen_insn_start(tcg_ctx, ctx->pc);
}
op = MASK_OP_MAJOR(ctx->opcode);

2
qemu/target-sparc/translate.c
View File

@ -2623,7 +2623,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
target_long simm;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(tcg_ctx, dc->pc);
tcg_gen_insn_start(tcg_ctx, dc->pc);
}
// Unicorn: trace this instruction on request

6
qemu/tcg/tcg-op.h
View File

@ -701,14 +701,14 @@ static inline void tcg_gen_concat32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 lo
#endif
/* debug info: write the PC of the corresponding QEMU CPU instruction */
static inline void tcg_gen_debug_insn_start(TCGContext *s, uint64_t pc)
static inline void tcg_gen_insn_start(TCGContext *s, uint64_t pc)
{
/* XXX: must really use a 32 bit size for TCGArg in all cases */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
tcg_gen_op2ii(s, INDEX_op_debug_insn_start,
tcg_gen_op2ii(s, INDEX_op_insn_start,
(uint32_t)(pc), (uint32_t)(pc >> 32));
#else
tcg_gen_op1i(s, INDEX_op_debug_insn_start, pc);
tcg_gen_op1i(s, INDEX_op_insn_start, pc);
#endif
}

4
qemu/tcg/tcg-opc.h
View File

@ -181,9 +181,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
/* QEMU specific */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
DEF(insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
#else
DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
#endif
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)

6
qemu/tcg/tcg.c
View File

@ -1034,7 +1034,7 @@ void tcg_dump_ops(TCGContext *s)
def = &s->tcg_op_defs[c];
args = &s->gen_opparam_buf[op->args];
if (c == INDEX_op_debug_insn_start) {
if (c == INDEX_op_insn_start) {
uint64_t pc;
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
pc = ((uint64_t)args[1] << 32) | args[0];
@ -1455,7 +1455,7 @@ static void tcg_liveness_analysis(TCGContext *s)
}
}
break;
case INDEX_op_debug_insn_start:
case INDEX_op_insn_start:
break;
case INDEX_op_discard:
/* mark the temporary as dead */
@ -2405,7 +2405,7 @@ static inline int tcg_gen_code_common(TCGContext *s,
case INDEX_op_movi_i64:
tcg_reg_alloc_movi(s, args, dead_args, sync_args);
break;
case INDEX_op_debug_insn_start:
case INDEX_op_insn_start:
break;
case INDEX_op_discard:
temp_dead(s, args[0]);

2
qemu/x86_64.h
View File

@ -2719,7 +2719,6 @@
#define tcg_gen_code_common tcg_gen_code_common_x86_64
#define tcg_gen_code_search_pc tcg_gen_code_search_pc_x86_64
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_x86_64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_x86_64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_x86_64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_x86_64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_x86_64
@ -2747,6 +2746,7 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
#define tcg_gen_insn_start tcg_gen_insn_start_x86_64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_x86_64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_x86_64