From b44de569f017fbd19b96947b81bf9aca6afed0aa Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 28 May 2019 19:14:29 -0400 Subject: [PATCH] target/riscv: Improve the scause logic No functional change, just making the code easier to read. Backports commit 16fdb8ff64374ed51b246437e13043039a8eb9f9 from qemu --- qemu/target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index c4dc6df6..56921d15 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -500,7 +500,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); env->mstatus = s; - env->scause = cause | ~(((target_ulong)-1) >> async); + env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); env->sepc = env->pc; env->sbadaddr = tval; env->pc = (env->stvec >> 2 << 2) +