From bc097bd2ae9871556abbe5ce69a5a22bf8584927 Mon Sep 17 00:00:00 2001 From: Corey Wharton Date: Thu, 30 Apr 2020 21:08:01 -0400 Subject: [PATCH] target/riscv: Add a sifive-e34 cpu type The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Backports commit d784733bf1875c1ba355c69739518f24d56f1260 from qemu --- qemu/target/riscv/cpu.c | 10 ++++++++++ qemu/target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index 415eb772..6834d643 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -155,6 +155,15 @@ static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *op set_feature(env, RISCV_FEATURE_PMP); } +static void rv32imafcu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) +{ + CPURISCVState *env = &RISCV_CPU(uc, obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_PMP); +} + #elif defined(TARGET_RISCV64) static void riscv_base64_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) @@ -389,6 +398,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), /* Deprecated */ DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index d84cd0d1..89f80e5e 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -39,6 +39,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")