target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions

Refactor disas_thumb2_insn() so that it generates the code for raising
an UNDEF exception for invalid insns, rather than returning a flag
which the caller must check to see if it needs to generate the UNDEF
code. This brings the function in to line with the behaviour of
disas_thumb_insn() and disas_arm_insn().

Backports commit 2eea841c11096e8dcc457b80e21f3fbdc32d2590 from qemu
This commit is contained in:
Peter Maydell 2018-03-06 08:49:18 -05:00 committed by Lioncash
parent 5fabebabee
commit bfd6d3e59b
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@ -9957,9 +9957,8 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
return 0; return 0;
} }
/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction /* Translate a 32-bit thumb instruction. */
is not legal. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t imm, shift, offset; uint32_t imm, shift, offset;
@ -11199,16 +11198,16 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* UNPREDICTABLE, unallocated hint or /* UNPREDICTABLE, unallocated hint or
* PLD/PLDW/PLI (literal) * PLD/PLDW/PLI (literal)
*/ */
return 0; return;
} }
if (op1 & 1) { if (op1 & 1) {
return 0; /* PLD/PLDW/PLI or unallocated hint */ return; /* PLD/PLDW/PLI or unallocated hint */
} }
if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
return 0; /* PLD/PLDW/PLI or unallocated hint */ return; /* PLD/PLDW/PLI or unallocated hint */
} }
/* UNDEF space, or an UNPREDICTABLE */ /* UNDEF space, or an UNPREDICTABLE */
return 1; goto illegal_op;
} }
} }
memidx = get_mem_index(s); memidx = get_mem_index(s);
@ -11334,9 +11333,10 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
default: default:
goto illegal_op; goto illegal_op;
} }
return 0; return;
illegal_op: illegal_op:
return 1; gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
} }
static void disas_thumb_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@ -12496,10 +12496,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
if (is_16bit) { if (is_16bit) {
disas_thumb_insn(dc, insn); disas_thumb_insn(dc, insn);
} else { } else {
if (disas_thumb2_insn(dc, insn)) { disas_thumb2_insn(dc, insn);
gen_exception_insn(dc, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(dc));
}
} }
/* Advance the Thumb condexec condition. */ /* Advance the Thumb condexec condition. */