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target/arm: Use vector infrastructure for aa64 multiplies

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Backports commit 0c7c55c492c918b6275baa3fee8b176c31465e3c from qemu
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Richard Henderson 2018-03-06 16:14:43 -05:00 committed by Lioncash
parent 955fec9300
commit c5c8488928
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 129 additions and 25 deletions
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154
qemu/target/arm/translate-a64.c
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@ -9889,6 +9889,66 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
}
}
static void gen_mla8_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u8(s, a, a, b);
gen_helper_neon_add_u8(s, d, d, a);
}
static void gen_mla16_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u16(s, a, a, b);
gen_helper_neon_add_u16(s, d, d, a);
}
static void gen_mla32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_mul_i32(s, a, a, b);
tcg_gen_add_i32(s, d, d, a);
}
static void gen_mla64_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_mul_i64(s, a, a, b);
tcg_gen_add_i64(s, d, d, a);
}
static void gen_mla_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
tcg_gen_mul_vec(s, vece, a, a, b);
tcg_gen_add_vec(s, vece, d, d, a);
}
static void gen_mls8_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u8(s, a, a, b);
gen_helper_neon_sub_u8(s, d, d, a);
}
static void gen_mls16_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u16(s, a, a, b);
gen_helper_neon_sub_u16(s, d, d, a);
}
static void gen_mls32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_mul_i32(s, a, a, b);
tcg_gen_sub_i32(s, d, d, a);
}
static void gen_mls64_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_mul_i64(s, a, a, b);
tcg_gen_sub_i64(s, d, d, a);
}
static void gen_mls_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
tcg_gen_mul_vec(s, vece, a, a, b);
tcg_gen_sub_vec(s, vece, d, d, a);
}
/* Integer op subgroup of C3.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{
@ -9907,6 +9967,52 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
static const GVecGen3 mla_op[4] = {
{ .fni4 = gen_mla8_i32,
.fniv = gen_mla_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_8 },
{ .fni4 = gen_mla16_i32,
.fniv = gen_mla_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_16 },
{ .fni4 = gen_mla32_i32,
.fniv = gen_mla_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_32 },
{ .fni8 = gen_mla64_i64,
.fniv = gen_mla_vec,
.opc = INDEX_op_mul_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.load_dest = true,
.vece = MO_64 },
};
static const GVecGen3 mls_op[4] = {
{ .fni4 = gen_mls8_i32,
.fniv = gen_mls_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_8 },
{ .fni4 = gen_mls16_i32,
.fniv = gen_mls_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_16 },
{ .fni4 = gen_mls32_i32,
.fniv = gen_mls_vec,
.opc = INDEX_op_mul_vec,
.load_dest = true,
.vece = MO_32 },
{ .fni8 = gen_mls64_i64,
.fniv = gen_mls_vec,
.opc = INDEX_op_mul_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.load_dest = true,
.vece = MO_64 },
};
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int is_q = extract32(insn, 30, 1);
@ -9965,6 +10071,19 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size);
}
return;
case 0x13: /* MUL, PMUL */
if (!u) { /* MUL */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
return;
}
break;
case 0x12: /* MLA, MLS */
if (u) {
gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]);
} else {
gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]);
}
return;
case 0x11:
if (!u) { /* CMTST */
gen_gvec_op3(s, is_q, rd, rn, rm, &cmtst_op[size]);
@ -10139,23 +10258,10 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
break;
}
case 0x13: /* MUL, PMUL */
if (u) {
/* PMUL */
assert(size == 0);
genfn = gen_helper_neon_mul_p8;
break;
}
/* fall through : MUL */
case 0x12: /* MLA, MLS */
{
static NeonGenTwoOpFn * const fns[3] = {
gen_helper_neon_mul_u8,
gen_helper_neon_mul_u16,
tcg_gen_mul_i32,
};
genfn = fns[size];
assert(u); /* PMUL */
assert(size == 0);
genfn = gen_helper_neon_mul_p8;
break;
}
case 0x16: /* SQDMULH, SQRDMULH */
{
static NeonGenTwoOpEnvFn * const fns[2][2] = {
@ -10176,18 +10282,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
}
if (opcode == 0xf || opcode == 0x12) {
/* SABA, UABA, MLA, MLS: accumulating ops */
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
{ tcg_gen_add_i32, tcg_gen_sub_i32 },
if (opcode == 0xf) {
/* SABA, UABA: accumulating ops */
static NeonGenTwoOpFn * const fns[3] = {
gen_helper_neon_add_u8,
gen_helper_neon_add_u16,
tcg_gen_add_i32,
};
bool is_sub = (opcode == 0x12 && u); /* MLS */
genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
genfn(tcg_ctx, tcg_res, tcg_op1, tcg_res);
fns[size](tcg_ctx, tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);