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target/mips: Add definition of nanoMIPS I7200 CPU

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Add definition of the first nanoMIPS processor in QEMU.

Backports commit d45942d908edee175a90f915ab92ac302eedf33a from qemu
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Stefan Markovic 2018-08-27 15:06:55 -04:00 committed by Lioncash
parent d53c021cea
commit c870339a10
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1 changed files with 50 additions and 0 deletions
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50
qemu/target/mips/translate_init.c
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@ -612,6 +612,56 @@ const mips_def_t mips_defs[] =
CPU_MIPS32R6 | ASE_MICROMIPS,
MMU_TYPE_R4000,
},
{
"I7200",
0x00010000,
MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
(1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
(4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
(4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
(1 << CP0C1_EP),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
(1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
(1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
(1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
(1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
(1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
(1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(2 << CP0C4_IE) | (1U << CP0C4_M),
0,
MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
(1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
(1 << CP0C5_UFE),
0,0,
0,
0,
32,
2,
0x3158FF1F,
0,
0,
(1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
(1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
0,
32,
32,
0,0,
0,0,
0,0,
0,0,
0,0,
0,
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE),
0,
CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
{
"R4000",