From ced883473741460f7755da3b0bce98051c49989d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Sat, 21 Mar 2020 13:14:36 -0400 Subject: [PATCH] target/arm: fix TCG leak for fcvt half->double When support for the AHP flag was added we inexplicably only freed the new temps in one of the two legs. Move those tcg_temp_free to the same level as the allocation to fix that leak. Backports commit aeab8e5eb220cc5ff84b0b68b9afccc611bf0fcd from qemu --- qemu/target/arm/translate-a64.c | 4 ++-- qemu/target/mips/op_helper.c | 8 ++------ 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index e57ede20..51dfcac3 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -6023,8 +6023,6 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx); gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); write_fp_sreg(s, rd, tcg_rd); - tcg_temp_free_ptr(tcg_ctx, tcg_fpst); - tcg_temp_free_i32(tcg_ctx, tcg_ahp); tcg_temp_free_i32(tcg_ctx, tcg_rd); } else { /* Half to double */ @@ -6034,6 +6032,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, tcg_temp_free_i64(tcg_ctx, tcg_rd); } tcg_temp_free_i32(tcg_ctx, tcg_rn); + tcg_temp_free_ptr(tcg_ctx, tcg_fpst); + tcg_temp_free_i32(tcg_ctx, tcg_ahp); break; } default: diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c index 981f0598..042d96c3 100644 --- a/qemu/target/mips/op_helper.c +++ b/qemu/target/mips/op_helper.c @@ -2545,17 +2545,13 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); uint8_t invMsgR = 0; uint32_t invMsgMMid = env->CP0_MemoryMapID; - CPUState *other_cs = first_cpu; #ifdef TARGET_MIPS64 invMsgR = extract64(arg, 62, 2); #endif - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid, - invAll, invVAMMid, invMMid, invVA); - } + global_invalidate_tlb(env, invMsgVPN2, invMsgR, invMsgMMid, + invAll, invVAMMid, invMMid, invVA); } /* Specials */