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target-arm: Enable the AArch32 ATS12NSO ops

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Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
* succeed at EL2 or EL3
* normal UNDEF trap from NS EL1
* trap to EL3 from S EL1 (only possible if EL3 is AArch64)

(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)

Backports commit 87562e4f4a2bdd028eef3549ce9cb4e7c83cb0bf from qemu
This commit is contained in:
Peter Maydell 2018-02-15 09:22:23 -05:00 committed by Lioncash
parent 2c4677ee5a
commit cf386519d2
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 11 additions and 5 deletions
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16
qemu/target-arm/helper.c
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@ -1467,12 +1467,17 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (ri->opc2 & 4) {
/* Other states are only available with TrustZone; in
* a non-TZ implementation these registers don't exist
* at all, which is an Uncategorized trap. This underdecoding
* is safe because the reginfo is NO_RAW.
/* The ATS12NSO* operations must trap to EL3 if executed in
* Secure EL1 (which can only happen if EL3 is AArch64).
* They are simply UNDEF if executed from NS EL1.
* They function normally from EL2 or EL3.
*/
return CP_ACCESS_TRAP_UNCATEGORIZED;
if (arm_current_el(env) == 1) {
if (arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
}
return CP_ACCESS_TRAP_UNCATEGORIZED;
}
}
return CP_ACCESS_OK;
}
@ -1646,6 +1651,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
{ offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) },
NULL, NULL, par_write },
#ifndef CONFIG_USER_ONLY
/* This underdecoding is safe because the reginfo is NO_RAW. */
{ "ATS", 15,7,8, 0,0,CP_ANY, 0,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
ats_access, NULL, ats_write },