yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-10-20 23:38:17 +02:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Rely on optimization within tcg_gen_gvec_or

Browse Source 
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.

Backports commit 2900847ff4c862887af750935a875059615f509a from qemu
This commit is contained in:
Richard Henderson 2019-02-15 17:50:20 -05:00 committed by Lioncash
parent bf9c8499ca
commit d147946edc
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
qemu/target/arm/translate-a64.c
View File

@ -10807,11 +10807,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
return; return;
case 2: /* ORR */ case 2: /* ORR */
if (rn == rm) { /* MOV */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
}
return; return;
case 3: /* ORN */ case 3: /* ORN */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);

6
qemu/target/arm/translate-sve.c
View File

@ -286,11 +286,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
{ {
if (a->rn == a->rm) { /* MOV */ return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
return do_mov_z(s, a->rd, a->rn);
} else {
return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
}
} }
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)

12
qemu/target/arm/translate.c
View File

@ -6456,15 +6456,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_gen_gvec_andc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs, tcg_gen_gvec_andc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size); vec_size, vec_size);
break; break;
case 2: case 2: /* VORR */
if (rn == rm) { tcg_gen_gvec_or(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
/* VMOV */ vec_size, vec_size);
tcg_gen_gvec_mov(tcg_ctx, 0, rd_ofs, rn_ofs, vec_size, vec_size);
} else {
/* VORR */
tcg_gen_gvec_or(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
}
break; break;
case 3: /* VORN */ case 3: /* VORN */
tcg_gen_gvec_orc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs, tcg_gen_gvec_orc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,