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target-arm: Move TB flags down to fill gap

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Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the
bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and
ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap.

Backports commit 647f767ba3b37fb229275086187e96242248a4ac from qemu
This commit is contained in:
Peter Maydell 2018-02-12 23:07:32 -05:00 committed by Lioncash
parent 63f04de43b
commit db727fad68
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-arm/cpu.h
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@ -1786,13 +1786,13 @@ static inline bool arm_singlestep_active(CPUARMState *env)
/* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime
*/
#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
/* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
#define ARM_TBFLAG_NS_SHIFT 22
#define ARM_TBFLAG_NS_SHIFT 19
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
/* Bit usage when in AArch64 state: currently we have no A64 specific bits */