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i386: Helpers to encode cache information consistently
Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us ensure consistency between cache information CPUID leaves, and make the existing inconsistencies in CPUID info more visible. Backports commit 7e3482f824809e1f6ffeb5bb8103ba27a7d1a52a from qemu
This commit is contained in:
Eduardo Habkost
Lioncash
parent
9c93f3f530
commit
db87beaaa6
@ -43,32 +43,240 @@
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#include "hw/i386/apic_internal.h"
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#endif
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/* Cache topology CPUID constants: */
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/* Helpers for building CPUID[2] descriptors: */
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/* CPUID Leaf 2 Descriptors */
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struct CPUID2CacheDescriptorInfo {
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enum CacheType type;
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int level;
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int size;
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int line_size;
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int associativity;
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};
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#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
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#define CPUID_2_L1I_32KB_8WAY_64B 0x30
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#define CPUID_2_L2_2MB_8WAY_64B 0x7d
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#define CPUID_2_L3_16MB_16WAY_64B 0x4d
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#define KiB 1024
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#define MiB (1024 * 1024)
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/*
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* Known CPUID 2 cache descriptors.
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* From Intel SDM Volume 2A, CPUID instruction
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*/
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struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
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[0x06] = { .level = 1, .type = ICACHE, .size = 8 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x08] = { .level = 1, .type = ICACHE, .size = 16 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x09] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x0A] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
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.associativity = 2, .line_size = 32, },
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[0x0C] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x0D] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x0E] = { .level = 1, .type = DCACHE, .size = 24 * KiB,
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.associativity = 6, .line_size = 64, },
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[0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
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.associativity = 2, .line_size = 64, },
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[0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
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.associativity = 8, .line_size = 64, },
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/* lines per sector is not supported cpuid2_cache_descriptor(),
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* so descriptors 0x22, 0x23 are not included
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*/
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[0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 16, .line_size = 64, },
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/* lines per sector is not supported cpuid2_cache_descriptor(),
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* so descriptors 0x25, 0x20 are not included
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*/
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[0x2C] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
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.associativity = 8, .line_size = 64, },
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[0x30] = { .level = 1, .type = ICACHE, .size = 32 * KiB,
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.associativity = 8, .line_size = 64, },
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[0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 4, .line_size = 32, },
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[0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 4, .line_size = 32, },
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[0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 4, .line_size = 32, },
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[0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
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.associativity = 4, .line_size = 64, },
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[0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
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.associativity = 8, .line_size = 64, },
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[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
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.associativity = 12, .line_size = 64, },
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/* Descriptor 0x49 depends on CPU family/model, so it is not included */
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[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
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.associativity = 12, .line_size = 64, },
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[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
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.associativity = 16, .line_size = 64, },
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[0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
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.associativity = 12, .line_size = 64, },
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[0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
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.associativity = 16, .line_size = 64, },
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[0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
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.associativity = 24, .line_size = 64, },
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[0x60] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
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.associativity = 8, .line_size = 64, },
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[0x66] = { .level = 1, .type = DCACHE, .size = 8 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x67] = { .level = 1, .type = DCACHE, .size = 16 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x68] = { .level = 1, .type = DCACHE, .size = 32 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 4, .line_size = 64, },
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/* lines per sector is not supported cpuid2_cache_descriptor(),
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* so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
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*/
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[0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 8, .line_size = 64, },
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[0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 2, .line_size = 64, },
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[0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 8, .line_size = 64, },
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[0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
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.associativity = 8, .line_size = 32, },
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[0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 8, .line_size = 32, },
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[0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 8, .line_size = 32, },
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[0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 8, .line_size = 32, },
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[0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 4, .line_size = 64, },
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[0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 8, .line_size = 64, },
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[0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
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.associativity = 4, .line_size = 64, },
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[0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 4, .line_size = 64, },
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[0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 4, .line_size = 64, },
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[0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
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.associativity = 8, .line_size = 64, },
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[0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 8, .line_size = 64, },
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[0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
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.associativity = 8, .line_size = 64, },
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[0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
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.associativity = 12, .line_size = 64, },
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[0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
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.associativity = 12, .line_size = 64, },
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[0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
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.associativity = 12, .line_size = 64, },
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[0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
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.associativity = 16, .line_size = 64, },
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[0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
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.associativity = 16, .line_size = 64, },
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[0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
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.associativity = 16, .line_size = 64, },
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[0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
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.associativity = 24, .line_size = 64, },
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[0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
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.associativity = 24, .line_size = 64, },
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[0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
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.associativity = 24, .line_size = 64, },
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};
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/*
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* "CPUID leaf 2 does not report cache descriptor information,
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* use CPUID leaf 4 to query cache parameters"
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*/
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#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
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/*
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* Return a CPUID 2 cache descriptor for a given cache.
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* If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
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*/
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static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
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{
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int i;
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assert(cache->size > 0);
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assert(cache->level > 0);
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assert(cache->line_size > 0);
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assert(cache->associativity > 0);
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for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
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struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
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if (d->level == cache->level && d->type == cache->type &&
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d->size == cache->size && d->line_size == cache->line_size &&
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d->associativity == cache->associativity) {
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return i;
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}
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}
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return CACHE_DESCRIPTOR_UNAVAILABLE;
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}
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/* CPUID Leaf 4 constants: */
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/* EAX: */
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#define CPUID_4_TYPE_DCACHE 1
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#define CPUID_4_TYPE_ICACHE 2
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#define CPUID_4_TYPE_UNIFIED 3
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#define CACHE_TYPE_D 1
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#define CACHE_TYPE_I 2
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#define CACHE_TYPE_UNIFIED 3
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#define CPUID_4_LEVEL(l) ((l) << 5)
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#define CACHE_LEVEL(l) (l << 5)
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#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
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#define CPUID_4_FULLY_ASSOC (1 << 9)
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#define CACHE_SELF_INIT_LEVEL (1 << 8)
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/* EDX: */
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#define CPUID_4_NO_INVD_SHARING (1 << 0)
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#define CPUID_4_INCLUSIVE (1 << 1)
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#define CPUID_4_COMPLEX_IDX (1 << 2)
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#define CACHE_NO_INVD_SHARING (1 << 0)
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#define CACHE_INCLUSIVE (1 << 1)
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#define CACHE_COMPLEX_IDX (1 << 2)
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/* Encode CacheType for CPUID[4].EAX */
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#define CACHE_TYPE(t) (((t) == DCACHE) ? CACHE_TYPE_D : \
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((t) == ICACHE) ? CACHE_TYPE_I : \
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((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
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0 /* Invalid value */)
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/* Encode cache info for CPUID[4] */
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static void encode_cache_cpuid4(CPUCacheInfo *cache,
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int num_apic_ids, int num_cores,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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assert(cache->size == cache->line_size * cache->associativity *
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cache->partitions * cache->sets);
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assert(num_apic_ids > 0);
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*eax = CACHE_TYPE(cache->type) |
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CACHE_LEVEL(cache->level) |
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(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
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((num_cores - 1) << 26) |
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((num_apic_ids - 1) << 14);
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assert(cache->line_size > 0);
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assert(cache->partitions > 0);
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assert(cache->associativity > 0);
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/* We don't implement fully-associative caches */
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assert(cache->associativity < cache->sets);
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*ebx = (cache->line_size - 1) |
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((cache->partitions - 1) << 12) |
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((cache->associativity - 1) << 22);
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assert(cache->sets > 0);
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*ecx = cache->sets - 1;
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*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
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(cache->inclusive ? CACHE_INCLUSIVE : 0) |
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(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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}
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/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
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static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
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{
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assert(cache->size % 1024 == 0);
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assert(cache->lines_per_tag > 0);
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assert(cache->associativity > 0);
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assert(cache->line_size > 0);
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return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
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(cache->lines_per_tag << 8) | (cache->line_size);
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}
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#define ASSOC_FULL 0xFF
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@ -86,57 +294,141 @@
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a == ASSOC_FULL ? 0xF : \
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0 /* invalid value */)
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/*
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* Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
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* @l3 can be NULL.
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*/
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static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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CPUCacheInfo *l3,
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uint32_t *ecx, uint32_t *edx)
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{
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assert(l2->size % 1024 == 0);
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assert(l2->associativity > 0);
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assert(l2->lines_per_tag > 0);
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assert(l2->line_size > 0);
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*ecx = ((l2->size / 1024) << 16) |
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(AMD_ENC_ASSOC(l2->associativity) << 12) |
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(l2->lines_per_tag << 8) | (l2->line_size);
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if (l3) {
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assert(l3->size % (512 * 1024) == 0);
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assert(l3->associativity > 0);
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assert(l3->lines_per_tag > 0);
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assert(l3->line_size > 0);
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*edx = ((l3->size / (512 * 1024)) << 18) |
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(AMD_ENC_ASSOC(l3->associativity) << 12) |
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(l3->lines_per_tag << 8) | (l3->line_size);
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} else {
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*edx = 0;
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}
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}
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/* Definitions of the hardcoded cache entries we expose: */
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/* L1 data cache: */
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#define L1D_LINE_SIZE 64
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#define L1D_ASSOCIATIVITY 8
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#define L1D_SETS 64
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#define L1D_PARTITIONS 1
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/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
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#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
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static CPUCacheInfo l1d_cache = {
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DCACHE,
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1,
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32 * KiB,
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64,
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8,
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1,
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64,
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0,
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1,
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true,
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};
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/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
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#define L1D_LINES_PER_TAG 1
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#define L1D_SIZE_KB_AMD 64
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#define L1D_ASSOCIATIVITY_AMD 2
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static CPUCacheInfo l1d_cache_amd = {
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DCACHE,
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1,
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64 * KiB,
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64,
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2,
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1,
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512,
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1,
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1,
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true,
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};
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/* L1 instruction cache: */
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#define L1I_LINE_SIZE 64
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#define L1I_ASSOCIATIVITY 8
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#define L1I_SETS 64
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#define L1I_PARTITIONS 1
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/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
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#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
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static CPUCacheInfo l1i_cache = {
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ICACHE,
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1,
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32 * KiB,
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64,
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8,
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1,
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64,
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true,
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};
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/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
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#define L1I_LINES_PER_TAG 1
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#define L1I_SIZE_KB_AMD 64
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#define L1I_ASSOCIATIVITY_AMD 2
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static CPUCacheInfo l1i_cache_amd = {
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ICACHE,
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1,
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64 * KiB,
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64,
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2,
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1,
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512,
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1,
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1,
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true,
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};
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/* Level 2 unified cache: */
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#define L2_LINE_SIZE 64
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#define L2_ASSOCIATIVITY 16
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#define L2_SETS 4096
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#define L2_PARTITIONS 1
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/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
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static CPUCacheInfo l2_cache = {
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UNIFIED_CACHE,
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2,
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4 * MiB,
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||||
64,
|
||||
16,
|
||||
1,
|
||||
4096,
|
||||
0,
|
||||
1,
|
||||
true,
|
||||
};
|
||||
|
||||
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
|
||||
#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
|
||||
static CPUCacheInfo l2_cache_cpuid2 = {
|
||||
UNIFIED_CACHE,
|
||||
2,
|
||||
2 * MiB,
|
||||
64,
|
||||
8,
|
||||
};
|
||||
|
||||
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
|
||||
#define L2_LINES_PER_TAG 1
|
||||
#define L2_SIZE_KB_AMD 512
|
||||
static CPUCacheInfo l2_cache_amd = {
|
||||
UNIFIED_CACHE,
|
||||
2,
|
||||
512 * KiB,
|
||||
64,
|
||||
16,
|
||||
1,
|
||||
512,
|
||||
1,
|
||||
};
|
||||
|
||||
/* Level 3 unified cache: */
|
||||
#define L3_SIZE_KB 0 /* disabled */
|
||||
#define L3_ASSOCIATIVITY 0 /* disabled */
|
||||
#define L3_LINES_PER_TAG 0 /* disabled */
|
||||
#define L3_LINE_SIZE 0 /* disabled */
|
||||
#define L3_N_LINE_SIZE 64
|
||||
#define L3_N_ASSOCIATIVITY 16
|
||||
#define L3_N_SETS 16384
|
||||
#define L3_N_PARTITIONS 1
|
||||
#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
|
||||
#define L3_N_LINES_PER_TAG 1
|
||||
#define L3_N_SIZE_KB_AMD 16384
|
||||
static CPUCacheInfo l3_cache = {
|
||||
UNIFIED_CACHE,
|
||||
3,
|
||||
16 * MiB,
|
||||
64,
|
||||
16,
|
||||
1,
|
||||
16384,
|
||||
1,
|
||||
true,
|
||||
false,
|
||||
true,
|
||||
true,
|
||||
};
|
||||
|
||||
/* TLB definitions: */
|
||||
|
||||
@ -3336,85 +3628,53 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
if (!cpu->enable_l3_cache) {
|
||||
*ecx = 0;
|
||||
} else {
|
||||
*ecx = L3_N_DESCRIPTOR;
|
||||
*ecx = cpuid2_cache_descriptor(&l3_cache);
|
||||
}
|
||||
*edx = (L1D_DESCRIPTOR << 16) | \
|
||||
(L1I_DESCRIPTOR << 8) | \
|
||||
(L2_DESCRIPTOR);
|
||||
*edx = (cpuid2_cache_descriptor(&l1d_cache) << 16) |
|
||||
(cpuid2_cache_descriptor(&l1i_cache) << 8) |
|
||||
(cpuid2_cache_descriptor(&l2_cache_cpuid2));
|
||||
break;
|
||||
case 4:
|
||||
/* cache info: needed for Core compatibility */
|
||||
if (cpu->cache_info_passthrough) {
|
||||
host_cpuid(index, count, eax, ebx, ecx, edx);
|
||||
/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
|
||||
*eax &= ~0xFC000000;
|
||||
if ((*eax & 31) && cs->nr_cores > 1) {
|
||||
*eax |= (cs->nr_cores - 1) << 26;
|
||||
}
|
||||
} else {
|
||||
*eax = 0;
|
||||
switch (count) {
|
||||
case 0: /* L1 dcache info */
|
||||
*eax |= CPUID_4_TYPE_DCACHE | \
|
||||
CPUID_4_LEVEL(1) | \
|
||||
CPUID_4_SELF_INIT_LEVEL;
|
||||
*ebx = (L1D_LINE_SIZE - 1) | \
|
||||
((L1D_PARTITIONS - 1) << 12) | \
|
||||
((L1D_ASSOCIATIVITY - 1) << 22);
|
||||
*ecx = L1D_SETS - 1;
|
||||
*edx = CPUID_4_NO_INVD_SHARING;
|
||||
encode_cache_cpuid4(&l1d_cache,
|
||||
1, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 1: /* L1 icache info */
|
||||
*eax |= CPUID_4_TYPE_ICACHE | \
|
||||
CPUID_4_LEVEL(1) | \
|
||||
CPUID_4_SELF_INIT_LEVEL;
|
||||
*ebx = (L1I_LINE_SIZE - 1) | \
|
||||
((L1I_PARTITIONS - 1) << 12) | \
|
||||
((L1I_ASSOCIATIVITY - 1) << 22);
|
||||
*ecx = L1I_SETS - 1;
|
||||
*edx = CPUID_4_NO_INVD_SHARING;
|
||||
encode_cache_cpuid4(&l1i_cache,
|
||||
1, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 2: /* L2 cache info */
|
||||
*eax |= CPUID_4_TYPE_UNIFIED | \
|
||||
CPUID_4_LEVEL(2) | \
|
||||
CPUID_4_SELF_INIT_LEVEL;
|
||||
if (cs->nr_threads > 1) {
|
||||
*eax |= (cs->nr_threads - 1) << 14;
|
||||
}
|
||||
*ebx = (L2_LINE_SIZE - 1) | \
|
||||
((L2_PARTITIONS - 1) << 12) | \
|
||||
((L2_ASSOCIATIVITY - 1) << 22);
|
||||
*ecx = L2_SETS - 1;
|
||||
*edx = CPUID_4_NO_INVD_SHARING;
|
||||
encode_cache_cpuid4(&l2_cache,
|
||||
cs->nr_threads, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 3: /* L3 cache info */
|
||||
if (!cpu->enable_l3_cache) {
|
||||
*eax = 0;
|
||||
*ebx = 0;
|
||||
*ecx = 0;
|
||||
*edx = 0;
|
||||
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
|
||||
if (cpu->enable_l3_cache) {
|
||||
encode_cache_cpuid4(&l3_cache,
|
||||
(1 << pkg_offset), cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
}
|
||||
*eax |= CPUID_4_TYPE_UNIFIED | \
|
||||
CPUID_4_LEVEL(3) | \
|
||||
CPUID_4_SELF_INIT_LEVEL;
|
||||
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
|
||||
*eax |= ((1 << pkg_offset) - 1) << 14;
|
||||
*ebx = (L3_N_LINE_SIZE - 1) | \
|
||||
((L3_N_PARTITIONS - 1) << 12) | \
|
||||
((L3_N_ASSOCIATIVITY - 1) << 22);
|
||||
*ecx = L3_N_SETS - 1;
|
||||
*edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
|
||||
break;
|
||||
/* fall through */
|
||||
default: /* end of info */
|
||||
*eax = 0;
|
||||
*ebx = 0;
|
||||
*ecx = 0;
|
||||
*edx = 0;
|
||||
*eax = *ebx = *ecx = *edx = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
|
||||
if ((*eax & 31) && cs->nr_cores > 1) {
|
||||
*eax |= (cs->nr_cores - 1) << 26;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
/* mwait info: needed for Core compatibility */
|
||||
@ -3609,10 +3869,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
|
||||
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
|
||||
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
|
||||
*ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
|
||||
(L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
|
||||
*edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
|
||||
(L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
|
||||
*ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
|
||||
*edx = encode_cache_cpuid80000005(&l1i_cache_amd);
|
||||
break;
|
||||
case 0x80000006:
|
||||
/* cache info (L2 cache) */
|
||||
@ -3628,18 +3886,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
(L2_DTLB_4K_ENTRIES << 16) | \
|
||||
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
|
||||
(L2_ITLB_4K_ENTRIES);
|
||||
*ecx = (L2_SIZE_KB_AMD << 16) | \
|
||||
(AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
|
||||
(L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
|
||||
if (!cpu->enable_l3_cache) {
|
||||
*edx = ((L3_SIZE_KB / 512) << 18) | \
|
||||
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
|
||||
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
|
||||
} else {
|
||||
*edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
|
||||
(AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
|
||||
(L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
|
||||
}
|
||||
encode_cache_cpuid80000006(&l2_cache_amd,
|
||||
cpu->enable_l3_cache ? &l3_cache : NULL,
|
||||
ecx, edx);
|
||||
break;
|
||||
case 0x80000007:
|
||||
*eax = 0;
|
||||
|
||||
@ -1002,6 +1002,57 @@ typedef enum TPRAccess {
|
||||
TPR_ACCESS_WRITE,
|
||||
} TPRAccess;
|
||||
|
||||
/* Cache information data structures: */
|
||||
|
||||
enum CacheType {
|
||||
DCACHE,
|
||||
ICACHE,
|
||||
UNIFIED_CACHE
|
||||
};
|
||||
|
||||
typedef struct CPUCacheInfo {
|
||||
enum CacheType type;
|
||||
uint8_t level;
|
||||
/* Size in bytes */
|
||||
uint32_t size;
|
||||
/* Line size, in bytes */
|
||||
uint16_t line_size;
|
||||
/*
|
||||
* Associativity.
|
||||
* Note: representation of fully-associative caches is not implemented
|
||||
*/
|
||||
uint8_t associativity;
|
||||
/* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
|
||||
uint8_t partitions;
|
||||
/* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
|
||||
uint32_t sets;
|
||||
/*
|
||||
* Lines per tag.
|
||||
* AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
|
||||
* (Is this synonym to @partitions?)
|
||||
*/
|
||||
uint8_t lines_per_tag;
|
||||
|
||||
/* Self-initializing cache */
|
||||
bool self_init;
|
||||
/*
|
||||
* WBINVD/INVD is not guaranteed to act upon lower level caches of
|
||||
* non-originating threads sharing this cache.
|
||||
* CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
|
||||
*/
|
||||
bool no_invd_sharing;
|
||||
/*
|
||||
* Cache is inclusive of lower cache levels.
|
||||
* CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
|
||||
*/
|
||||
bool inclusive;
|
||||
/*
|
||||
* A complex function is used to index the cache, potentially using all
|
||||
* address bits. CPUID[4].EDX[bit 2].
|
||||
*/
|
||||
bool complex_indexing;
|
||||
} CPUCacheInfo;
|
||||
|
||||
typedef struct CPUX86State {
|
||||
/* standard registers */
|
||||
target_ulong regs[CPU_NB_REGS];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user