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exec.c: Add new address_space_ld*/st* functions

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Add new address_space_ld*/st* functions which allow transaction
attributes and error reporting for basic load and stores. These
are named to be in line with the address_space_read/write/rw
buffer operations.

The existing ld/st*_phys functions are now wrappers around
the new functions.

Backports commit 500131154d677930fce35ec3a6f0b5a26bcd2973 from qemu
This commit is contained in:
Peter Maydell 2018-02-12 19:17:29 -05:00 committed by Lioncash
parent b94c89e559
commit df0fac6b6a
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
16 changed files with 657 additions and 99 deletions
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21
qemu/aarch64.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_AARCH64_H
#define UNICORN_AUTOGEN_AARCH64_H
#define address_space_ldub address_space_ldub_aarch64
#define address_space_lduw address_space_lduw_aarch64
#define address_space_lduw_le address_space_lduw_le_aarch64
#define address_space_lduw_be address_space_lduw_be_aarch64
#define address_space_ldl address_space_ldl_aarch64
#define address_space_ldl_le address_space_ldl_le_aarch64
#define address_space_ldl_be address_space_ldl_be_aarch64
#define address_space_ldq address_space_ldq_aarch64
#define address_space_ldq_le address_space_ldq_le_aarch64
#define address_space_ldq_be address_space_ldq_be_aarch64
#define address_space_stb address_space_stb_aarch64
#define address_space_stw address_space_stw_aarch64
#define address_space_stw_le address_space_stw_le_aarch64
#define address_space_stw_be address_space_stw_be_aarch64
#define address_space_stl address_space_stl_aarch64
#define address_space_stl_le address_space_stl_le_aarch64
#define address_space_stl_notdirty address_space_stl_notdirty_aarch64
#define address_space_stl_be address_space_stl_be_aarch64
#define address_space_stq address_space_stq_aarch64
#define address_space_stq_le address_space_stq_le_aarch64
#define address_space_stq_be address_space_stq_be_aarch64
#define arm_release arm_release_aarch64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_aarch64

21
qemu/aarch64eb.h
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@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_AARCH64EB_H
#define UNICORN_AUTOGEN_AARCH64EB_H
#define address_space_ldub address_space_ldub_aarch64eb
#define address_space_lduw address_space_lduw_aarch64eb
#define address_space_lduw_le address_space_lduw_le_aarch64eb
#define address_space_lduw_be address_space_lduw_be_aarch64eb
#define address_space_ldl address_space_ldl_aarch64eb
#define address_space_ldl_le address_space_ldl_le_aarch64eb
#define address_space_ldl_be address_space_ldl_be_aarch64eb
#define address_space_ldq address_space_ldq_aarch64eb
#define address_space_ldq_le address_space_ldq_le_aarch64eb
#define address_space_ldq_be address_space_ldq_be_aarch64eb
#define address_space_stb address_space_stb_aarch64eb
#define address_space_stw address_space_stw_aarch64eb
#define address_space_stw_le address_space_stw_le_aarch64eb
#define address_space_stw_be address_space_stw_be_aarch64eb
#define address_space_stl address_space_stl_aarch64eb
#define address_space_stl_le address_space_stl_le_aarch64eb
#define address_space_stl_notdirty address_space_stl_notdirty_aarch64eb
#define address_space_stl_be address_space_stl_be_aarch64eb
#define address_space_stq address_space_stq_aarch64eb
#define address_space_stq_le address_space_stq_le_aarch64eb
#define address_space_stq_be address_space_stq_be_aarch64eb
#define arm_release arm_release_aarch64eb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64eb
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_aarch64eb

21
qemu/arm.h
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@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_ARM_H
#define UNICORN_AUTOGEN_ARM_H
#define address_space_ldub address_space_ldub_arm
#define address_space_lduw address_space_lduw_arm
#define address_space_lduw_le address_space_lduw_le_arm
#define address_space_lduw_be address_space_lduw_be_arm
#define address_space_ldl address_space_ldl_arm
#define address_space_ldl_le address_space_ldl_le_arm
#define address_space_ldl_be address_space_ldl_be_arm
#define address_space_ldq address_space_ldq_arm
#define address_space_ldq_le address_space_ldq_le_arm
#define address_space_ldq_be address_space_ldq_be_arm
#define address_space_stb address_space_stb_arm
#define address_space_stw address_space_stw_arm
#define address_space_stw_le address_space_stw_le_arm
#define address_space_stw_be address_space_stw_be_arm
#define address_space_stl address_space_stl_arm
#define address_space_stl_le address_space_stl_le_arm
#define address_space_stl_notdirty address_space_stl_notdirty_arm
#define address_space_stl_be address_space_stl_be_arm
#define address_space_stq address_space_stq_arm
#define address_space_stq_le address_space_stq_le_arm
#define address_space_stq_be address_space_stq_be_arm
#define arm_release arm_release_arm
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_arm
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_arm

21
qemu/armeb.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_ARMEB_H
#define UNICORN_AUTOGEN_ARMEB_H
#define address_space_ldub address_space_ldub_armeb
#define address_space_lduw address_space_lduw_armeb
#define address_space_lduw_le address_space_lduw_le_armeb
#define address_space_lduw_be address_space_lduw_be_armeb
#define address_space_ldl address_space_ldl_armeb
#define address_space_ldl_le address_space_ldl_le_armeb
#define address_space_ldl_be address_space_ldl_be_armeb
#define address_space_ldq address_space_ldq_armeb
#define address_space_ldq_le address_space_ldq_le_armeb
#define address_space_ldq_be address_space_ldq_be_armeb
#define address_space_stb address_space_stb_armeb
#define address_space_stw address_space_stw_armeb
#define address_space_stw_le address_space_stw_le_armeb
#define address_space_stw_be address_space_stw_be_armeb
#define address_space_stl address_space_stl_armeb
#define address_space_stl_le address_space_stl_le_armeb
#define address_space_stl_notdirty address_space_stl_notdirty_armeb
#define address_space_stl_be address_space_stl_be_armeb
#define address_space_stq address_space_stq_armeb
#define address_space_stq_le address_space_stq_le_armeb
#define address_space_stq_be address_space_stq_be_armeb
#define arm_release arm_release_armeb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_armeb
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_armeb

395
qemu/exec.c
View File

@ -1976,20 +1976,22 @@ void cpu_physical_memory_unmap(AddressSpace *as, void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs,
MemTxResult *result,
enum device_endian endian)
{
uint8_t *ptr;
uint64_t val;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
memory_region_dispatch_read(mr, addr1, &val, 4,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@ -2005,51 +2007,78 @@ static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
& TARGET_PAGE_MASK)
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = ldl_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = ldl_be_p(ptr);
break;
default:
val = ldl_p(ptr);
break;
case DEVICE_LITTLE_ENDIAN:
val = ldl_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = ldl_be_p(ptr);
break;
default:
val = ldl_p(ptr);
break;
}
r = MEMTX_OK;
}
if (result) {
*result = r;
}
return val;
}
uint32_t address_space_ldl(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldl_internal(as, addr, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldl_internal(as, addr, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldl_internal(as, addr, attrs, result,
DEVICE_BIG_ENDIAN);
}
uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* warning: addr must be aligned */
static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs,
MemTxResult *result,
enum device_endian endian)
{
uint8_t *ptr;
uint64_t val;
MemoryRegion *mr;
hwaddr l = 8;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l,
false);
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
memory_region_dispatch_read(mr, addr1, &val, 8,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
@ -2065,59 +2094,98 @@ static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
& TARGET_PAGE_MASK)
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = ldq_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = ldq_be_p(ptr);
break;
default:
val = ldq_p(ptr);
break;
case DEVICE_LITTLE_ENDIAN:
val = ldq_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = ldq_be_p(ptr);
break;
default:
val = ldq_p(ptr);
break;
}
r = MEMTX_OK;
}
if (result) {
*result = r;
}
return val;
}
uint64_t address_space_ldq(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldq_internal(as, addr, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldq_internal(as, addr, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_ldq_internal(as, addr, attrs, result,
DEVICE_BIG_ENDIAN);
}
uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* XXX: optimize */
uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
uint8_t val;
address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0);
MemTxResult r;
r = address_space_rw(as, addr, attrs, &val, 1, 0);
if (result) {
*result = r;
}
return val;
}
uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* warning: addr must be aligned */
static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
static inline uint32_t address_space_lduw_internal(AddressSpace *as,
hwaddr addr,
MemTxAttrs attrs,
MemTxResult *result,
enum device_endian endian)
{
uint8_t *ptr;
uint64_t val;
MemoryRegion *mr;
hwaddr l = 2;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l,
false);
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
memory_region_dispatch_read(mr, addr1, &val, 2,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@ -2133,69 +2201,107 @@ static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
& TARGET_PAGE_MASK)
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = lduw_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = lduw_be_p(ptr);
break;
default:
val = lduw_p(ptr);
break;
case DEVICE_LITTLE_ENDIAN:
val = lduw_le_p(ptr);
break;
case DEVICE_BIG_ENDIAN:
val = lduw_be_p(ptr);
break;
default:
val = lduw_p(ptr);
break;
}
r = MEMTX_OK;
}
if (result) {
*result = r;
}
return val;
}
uint32_t address_space_lduw(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_lduw_internal(as, addr, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_lduw_internal(as, addr, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
return address_space_lduw_internal(as, addr, attrs, result,
DEVICE_BIG_ENDIAN);
}
uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l,
true);
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
memory_region_dispatch_write(mr, addr1, val, 4,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
} else {
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(as->uc, addr1);
stl_p(ptr, val);
r = MEMTX_OK;
}
if (result) {
*result = r;
}
}
void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* warning: addr must be aligned */
static inline void stl_phys_internal(AddressSpace *as,
hwaddr addr, uint32_t val,
enum device_endian endian)
static inline void address_space_stl_internal(AddressSpace *as,
hwaddr addr, uint32_t val,
MemTxAttrs attrs,
MemTxResult *result,
enum device_endian endian)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l,
true);
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@ -2206,58 +2312,96 @@ static inline void stl_phys_internal(AddressSpace *as,
val = bswap32(val);
}
#endif
memory_region_dispatch_write(mr, addr1, val, 4,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
} else {
/* RAM case */
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(as->uc, addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
stl_le_p(ptr, val);
break;
case DEVICE_BIG_ENDIAN:
stl_be_p(ptr, val);
break;
default:
stl_p(ptr, val);
break;
case DEVICE_LITTLE_ENDIAN:
stl_le_p(ptr, val);
break;
case DEVICE_BIG_ENDIAN:
stl_be_p(ptr, val);
break;
default:
stl_p(ptr, val);
break;
}
invalidate_and_set_dirty(mr->uc, addr1, 4);
r = MEMTX_OK;
}
if (result) {
*result = r;
}
}
void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stl_internal(as, addr, val, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stl_internal(as, addr, val, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stl_internal(as, addr, val, attrs, result,
DEVICE_BIG_ENDIAN);
}
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* XXX: optimize */
void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
uint8_t v = val;
address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1);
MemTxResult r;
r = address_space_rw(as, addr, attrs, &v, 1, 1);
if (result) {
*result = r;
}
}
void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* warning: addr must be aligned */
static inline void stw_phys_internal(AddressSpace *as,
hwaddr addr, uint32_t val,
enum device_endian endian)
static inline void address_space_stw_internal(AddressSpace *as,
hwaddr addr, uint32_t val,
MemTxAttrs attrs,
MemTxResult *result,
enum device_endian endian)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 2;
hwaddr addr1;
MemTxResult r;
mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
@ -2270,59 +2414,112 @@ static inline void stw_phys_internal(AddressSpace *as,
val = bswap16(val);
}
#endif
memory_region_dispatch_write(mr, addr1, val, 2,
MEMTXATTRS_UNSPECIFIED);
r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
} else {
/* RAM case */
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(as->uc, addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
stw_le_p(ptr, val);
break;
case DEVICE_BIG_ENDIAN:
stw_be_p(ptr, val);
break;
default:
stw_p(ptr, val);
break;
case DEVICE_LITTLE_ENDIAN:
stw_le_p(ptr, val);
break;
case DEVICE_BIG_ENDIAN:
stw_be_p(ptr, val);
break;
default:
stw_p(ptr, val);
break;
}
invalidate_and_set_dirty(as->uc, addr1, 2);
r = MEMTX_OK;
}
if (result) {
*result = r;
}
}
void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stw_internal(as, addr, val, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stw_internal(as, addr, val, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result)
{
address_space_stw_internal(as, addr, val, attrs, result,
DEVICE_BIG_ENDIAN);
}
void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* XXX: optimize */
void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result)
{
MemTxResult r;
val = tswap64(val);
r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
if (result) {
*result = r;
}
}
void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result)
{
MemTxResult r;
val = cpu_to_le64(val);
r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
if (result) {
*result = r;
}
}
void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result)
{
MemTxResult r;
val = cpu_to_be64(val);
r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
if (result) {
*result = r;
}
}
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
}
/* virtual memory access for debug (includes writing to ROM) */

21
qemu/header_gen.py
View File

@ -7,6 +7,27 @@
import sys
symbols = (
'address_space_ldub',
'address_space_lduw',
'address_space_lduw_le',
'address_space_lduw_be',
'address_space_ldl',
'address_space_ldl_le',
'address_space_ldl_be',
'address_space_ldq',
'address_space_ldq_le',
'address_space_ldq_be',
'address_space_stb',
'address_space_stw',
'address_space_stw_le',
'address_space_stw_be',
'address_space_stl',
'address_space_stl_le',
'address_space_stl_notdirty',
'address_space_stl_be',
'address_space_stq',
'address_space_stq_le',
'address_space_stq_be',
'arm_release',
'aarch64_sync_32_to_64',
'aarch64_sync_64_to_32',

67
qemu/include/exec/memory.h
View File

@ -852,6 +852,73 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
uint8_t *buf, int len);
/**
* address_space_ld*: load from an address space
* address_space_st*: store to an address space
*
* These functions perform a load or store of the byte, word,
* longword or quad to the specified address within the AddressSpace.
* The _le suffixed functions treat the data as little endian;
* _be indicates big endian; no suffix indicates "same endianness
* as guest CPU".
*
* The "guest CPU endianness" accessors are deprecated for use outside
* target-* code; devices should be CPU-agnostic and use either the LE
* or the BE accessors.
*
* @as #AddressSpace to be accessed
* @addr: address within that address space
* @val: data value, for stores
* @attrs: memory transaction attributes
* @result: location to write the success/failure of the transaction;
* if NULL, this information is discarded
*/
uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result);
#ifdef NEED_CPU_H
uint32_t address_space_lduw(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint32_t address_space_ldl(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
uint64_t address_space_ldq(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val,
MemTxAttrs attrs, MemTxResult *result);
void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
MemTxAttrs attrs, MemTxResult *result);
#endif
/* address_space_translate: translate an address range into an address space
* into a MemoryRegion and an address range into that section
*

21
qemu/m68k.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_M68K_H
#define UNICORN_AUTOGEN_M68K_H
#define address_space_ldub address_space_ldub_m68k
#define address_space_lduw address_space_lduw_m68k
#define address_space_lduw_le address_space_lduw_le_m68k
#define address_space_lduw_be address_space_lduw_be_m68k
#define address_space_ldl address_space_ldl_m68k
#define address_space_ldl_le address_space_ldl_le_m68k
#define address_space_ldl_be address_space_ldl_be_m68k
#define address_space_ldq address_space_ldq_m68k
#define address_space_ldq_le address_space_ldq_le_m68k
#define address_space_ldq_be address_space_ldq_be_m68k
#define address_space_stb address_space_stb_m68k
#define address_space_stw address_space_stw_m68k
#define address_space_stw_le address_space_stw_le_m68k
#define address_space_stw_be address_space_stw_be_m68k
#define address_space_stl address_space_stl_m68k
#define address_space_stl_le address_space_stl_le_m68k
#define address_space_stl_notdirty address_space_stl_notdirty_m68k
#define address_space_stl_be address_space_stl_be_m68k
#define address_space_stq address_space_stq_m68k
#define address_space_stq_le address_space_stq_le_m68k
#define address_space_stq_be address_space_stq_be_m68k
#define arm_release arm_release_m68k
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_m68k
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_m68k

21
qemu/mips.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_MIPS_H
#define UNICORN_AUTOGEN_MIPS_H
#define address_space_ldub address_space_ldub_mips
#define address_space_lduw address_space_lduw_mips
#define address_space_lduw_le address_space_lduw_le_mips
#define address_space_lduw_be address_space_lduw_be_mips
#define address_space_ldl address_space_ldl_mips
#define address_space_ldl_le address_space_ldl_le_mips
#define address_space_ldl_be address_space_ldl_be_mips
#define address_space_ldq address_space_ldq_mips
#define address_space_ldq_le address_space_ldq_le_mips
#define address_space_ldq_be address_space_ldq_be_mips
#define address_space_stb address_space_stb_mips
#define address_space_stw address_space_stw_mips
#define address_space_stw_le address_space_stw_le_mips
#define address_space_stw_be address_space_stw_be_mips
#define address_space_stl address_space_stl_mips
#define address_space_stl_le address_space_stl_le_mips
#define address_space_stl_notdirty address_space_stl_notdirty_mips
#define address_space_stl_be address_space_stl_be_mips
#define address_space_stq address_space_stq_mips
#define address_space_stq_le address_space_stq_le_mips
#define address_space_stq_be address_space_stq_be_mips
#define arm_release arm_release_mips
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips

21
qemu/mips64.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_MIPS64_H
#define UNICORN_AUTOGEN_MIPS64_H
#define address_space_ldub address_space_ldub_mips64
#define address_space_lduw address_space_lduw_mips64
#define address_space_lduw_le address_space_lduw_le_mips64
#define address_space_lduw_be address_space_lduw_be_mips64
#define address_space_ldl address_space_ldl_mips64
#define address_space_ldl_le address_space_ldl_le_mips64
#define address_space_ldl_be address_space_ldl_be_mips64
#define address_space_ldq address_space_ldq_mips64
#define address_space_ldq_le address_space_ldq_le_mips64
#define address_space_ldq_be address_space_ldq_be_mips64
#define address_space_stb address_space_stb_mips64
#define address_space_stw address_space_stw_mips64
#define address_space_stw_le address_space_stw_le_mips64
#define address_space_stw_be address_space_stw_be_mips64
#define address_space_stl address_space_stl_mips64
#define address_space_stl_le address_space_stl_le_mips64
#define address_space_stl_notdirty address_space_stl_notdirty_mips64
#define address_space_stl_be address_space_stl_be_mips64
#define address_space_stq address_space_stq_mips64
#define address_space_stq_le address_space_stq_le_mips64
#define address_space_stq_be address_space_stq_be_mips64
#define arm_release arm_release_mips64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips64

21
qemu/mips64el.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_MIPS64EL_H
#define UNICORN_AUTOGEN_MIPS64EL_H
#define address_space_ldub address_space_ldub_mips64el
#define address_space_lduw address_space_lduw_mips64el
#define address_space_lduw_le address_space_lduw_le_mips64el
#define address_space_lduw_be address_space_lduw_be_mips64el
#define address_space_ldl address_space_ldl_mips64el
#define address_space_ldl_le address_space_ldl_le_mips64el
#define address_space_ldl_be address_space_ldl_be_mips64el
#define address_space_ldq address_space_ldq_mips64el
#define address_space_ldq_le address_space_ldq_le_mips64el
#define address_space_ldq_be address_space_ldq_be_mips64el
#define address_space_stb address_space_stb_mips64el
#define address_space_stw address_space_stw_mips64el
#define address_space_stw_le address_space_stw_le_mips64el
#define address_space_stw_be address_space_stw_be_mips64el
#define address_space_stl address_space_stl_mips64el
#define address_space_stl_le address_space_stl_le_mips64el
#define address_space_stl_notdirty address_space_stl_notdirty_mips64el
#define address_space_stl_be address_space_stl_be_mips64el
#define address_space_stq address_space_stq_mips64el
#define address_space_stq_le address_space_stq_le_mips64el
#define address_space_stq_be address_space_stq_be_mips64el
#define arm_release arm_release_mips64el
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64el
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips64el

21
qemu/mipsel.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_MIPSEL_H
#define UNICORN_AUTOGEN_MIPSEL_H
#define address_space_ldub address_space_ldub_mipsel
#define address_space_lduw address_space_lduw_mipsel
#define address_space_lduw_le address_space_lduw_le_mipsel
#define address_space_lduw_be address_space_lduw_be_mipsel
#define address_space_ldl address_space_ldl_mipsel
#define address_space_ldl_le address_space_ldl_le_mipsel
#define address_space_ldl_be address_space_ldl_be_mipsel
#define address_space_ldq address_space_ldq_mipsel
#define address_space_ldq_le address_space_ldq_le_mipsel
#define address_space_ldq_be address_space_ldq_be_mipsel
#define address_space_stb address_space_stb_mipsel
#define address_space_stw address_space_stw_mipsel
#define address_space_stw_le address_space_stw_le_mipsel
#define address_space_stw_be address_space_stw_be_mipsel
#define address_space_stl address_space_stl_mipsel
#define address_space_stl_le address_space_stl_le_mipsel
#define address_space_stl_notdirty address_space_stl_notdirty_mipsel
#define address_space_stl_be address_space_stl_be_mipsel
#define address_space_stq address_space_stq_mipsel
#define address_space_stq_le address_space_stq_le_mipsel
#define address_space_stq_be address_space_stq_be_mipsel
#define arm_release arm_release_mipsel
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mipsel
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mipsel

21
qemu/powerpc.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_POWERPC_H
#define UNICORN_AUTOGEN_POWERPC_H
#define address_space_ldub address_space_ldub_powerpc
#define address_space_lduw address_space_lduw_powerpc
#define address_space_lduw_le address_space_lduw_le_powerpc
#define address_space_lduw_be address_space_lduw_be_powerpc
#define address_space_ldl address_space_ldl_powerpc
#define address_space_ldl_le address_space_ldl_le_powerpc
#define address_space_ldl_be address_space_ldl_be_powerpc
#define address_space_ldq address_space_ldq_powerpc
#define address_space_ldq_le address_space_ldq_le_powerpc
#define address_space_ldq_be address_space_ldq_be_powerpc
#define address_space_stb address_space_stb_powerpc
#define address_space_stw address_space_stw_powerpc
#define address_space_stw_le address_space_stw_le_powerpc
#define address_space_stw_be address_space_stw_be_powerpc
#define address_space_stl address_space_stl_powerpc
#define address_space_stl_le address_space_stl_le_powerpc
#define address_space_stl_notdirty address_space_stl_notdirty_powerpc
#define address_space_stl_be address_space_stl_be_powerpc
#define address_space_stq address_space_stq_powerpc
#define address_space_stq_le address_space_stq_le_powerpc
#define address_space_stq_be address_space_stq_be_powerpc
#define arm_release arm_release_powerpc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_powerpc
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_powerpc

21
qemu/sparc.h
View File

@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_SPARC_H
#define UNICORN_AUTOGEN_SPARC_H
#define address_space_ldub address_space_ldub_sparc
#define address_space_lduw address_space_lduw_sparc
#define address_space_lduw_le address_space_lduw_le_sparc
#define address_space_lduw_be address_space_lduw_be_sparc
#define address_space_ldl address_space_ldl_sparc
#define address_space_ldl_le address_space_ldl_le_sparc
#define address_space_ldl_be address_space_ldl_be_sparc
#define address_space_ldq address_space_ldq_sparc
#define address_space_ldq_le address_space_ldq_le_sparc
#define address_space_ldq_be address_space_ldq_be_sparc
#define address_space_stb address_space_stb_sparc
#define address_space_stw address_space_stw_sparc
#define address_space_stw_le address_space_stw_le_sparc
#define address_space_stw_be address_space_stw_be_sparc
#define address_space_stl address_space_stl_sparc
#define address_space_stl_le address_space_stl_le_sparc
#define address_space_stl_notdirty address_space_stl_notdirty_sparc
#define address_space_stl_be address_space_stl_be_sparc
#define address_space_stq address_space_stq_sparc
#define address_space_stq_le address_space_stq_le_sparc
#define address_space_stq_be address_space_stq_be_sparc
#define arm_release arm_release_sparc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_sparc

21
qemu/sparc64.h
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@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_SPARC64_H
#define UNICORN_AUTOGEN_SPARC64_H
#define address_space_ldub address_space_ldub_sparc64
#define address_space_lduw address_space_lduw_sparc64
#define address_space_lduw_le address_space_lduw_le_sparc64
#define address_space_lduw_be address_space_lduw_be_sparc64
#define address_space_ldl address_space_ldl_sparc64
#define address_space_ldl_le address_space_ldl_le_sparc64
#define address_space_ldl_be address_space_ldl_be_sparc64
#define address_space_ldq address_space_ldq_sparc64
#define address_space_ldq_le address_space_ldq_le_sparc64
#define address_space_ldq_be address_space_ldq_be_sparc64
#define address_space_stb address_space_stb_sparc64
#define address_space_stw address_space_stw_sparc64
#define address_space_stw_le address_space_stw_le_sparc64
#define address_space_stw_be address_space_stw_be_sparc64
#define address_space_stl address_space_stl_sparc64
#define address_space_stl_le address_space_stl_le_sparc64
#define address_space_stl_notdirty address_space_stl_notdirty_sparc64
#define address_space_stl_be address_space_stl_be_sparc64
#define address_space_stq address_space_stq_sparc64
#define address_space_stq_le address_space_stq_le_sparc64
#define address_space_stq_be address_space_stq_be_sparc64
#define arm_release arm_release_sparc64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_sparc64

21
qemu/x86_64.h
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@ -1,6 +1,27 @@
/* Autogen header for Unicorn Engine - DONOT MODIFY */
#ifndef UNICORN_AUTOGEN_X86_64_H
#define UNICORN_AUTOGEN_X86_64_H
#define address_space_ldub address_space_ldub_x86_64
#define address_space_lduw address_space_lduw_x86_64
#define address_space_lduw_le address_space_lduw_le_x86_64
#define address_space_lduw_be address_space_lduw_be_x86_64
#define address_space_ldl address_space_ldl_x86_64
#define address_space_ldl_le address_space_ldl_le_x86_64
#define address_space_ldl_be address_space_ldl_be_x86_64
#define address_space_ldq address_space_ldq_x86_64
#define address_space_ldq_le address_space_ldq_le_x86_64
#define address_space_ldq_be address_space_ldq_be_x86_64
#define address_space_stb address_space_stb_x86_64
#define address_space_stw address_space_stw_x86_64
#define address_space_stw_le address_space_stw_le_x86_64
#define address_space_stw_be address_space_stw_be_x86_64
#define address_space_stl address_space_stl_x86_64
#define address_space_stl_le address_space_stl_le_x86_64
#define address_space_stl_notdirty address_space_stl_notdirty_x86_64
#define address_space_stl_be address_space_stl_be_x86_64
#define address_space_stq address_space_stq_x86_64
#define address_space_stq_le address_space_stq_le_x86_64
#define address_space_stq_be address_space_stq_be_x86_64
#define arm_release arm_release_x86_64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_x86_64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_x86_64