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target-arm: add SDER definition

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Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for
register storage.

Backports commit 144634ae6c1618dcee6aced9c0d4427844154091 from qemu
This commit is contained in:
Greg Bellows 2018-02-11 19:01:36 -05:00 committed by Lioncash
parent 461944980c
commit e49d9d3f30
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2 changed files with 7 additions and 0 deletions
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1
qemu/target-arm/cpu.h
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@ -183,6 +183,7 @@ typedef struct CPUARMState {
uint64_t c1_sys; /* System control register. */
uint64_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint64_t sder; /* Secure debug enable register. */
uint32_t nsacr; /* Non-secure access control register. */
uint64_t ttbr0_el1; /* MMU translation table base 0. */
uint64_t ttbr1_el1; /* MMU translation table base 1. */

6
qemu/target-arm/helper.c
View File

@ -1994,6 +1994,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "SCR", 15,1,1, 0,0,0, 0,
ARM_CP_NO_MIGRATE, PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
NULL, NULL, scr_write, NULL, NULL, arm_cp_reset_ignore },
{ "SDER32_EL3", 0,1,1, 3,6,1, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0,
offsetof(CPUARMState, cp15.sder) },
{ "SDER", 15,1,1, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0,
offsetoflow32(CPUARMState, cp15.sder) },
/* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
{ "NSACR", 15,1,1, 0,0,2, 0,0,
PL3_W | PL1_R, 0, NULL, 0,