From e54a2b65c018536b6c074dcf0fd595e2fb40161e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 8 Oct 2018 11:08:05 -0400 Subject: [PATCH] softfloat: Specialize udiv_qrnnd for ppc64 The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Backports commit 27ae5109a2ba8b6b679cce3e03e16570a34390a0 from qemu --- qemu/fpu/softfloat-macros.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qemu/fpu/softfloat-macros.h b/qemu/fpu/softfloat-macros.h index bc1c6ec6..9216992d 100644 --- a/qemu/fpu/softfloat-macros.h +++ b/qemu/fpu/softfloat-macros.h @@ -647,6 +647,22 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r = n >> 64; return n; +#elif defined(_ARCH_PPC64) + /* From Power ISA 3.0B, programming note for divdeu. */ + uint64_t q1, q2, Q, r1, r2, R; + asm("divdeu %0,%2,%4; divdu %1,%3,%4" + : "=&r"(q1), "=r"(q2) + : "r"(n1), "r"(n0), "r"(d)); + r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ + r2 = n0 - (q2 * d); + Q = q1 + q2; + R = r1 + r2; + if (R >= d || R < r2) { /* overflow implies R > d */ + Q += 1; + R -= d; + } + *r = R; + return Q; #else uint64_t d0, d1, q0, q1, r1, r0, m;