diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 6bcaef38..31dcba33 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -2477,6 +2477,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       PL2_RW, 0, NULL, 0 },
     { "HMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
       PL2_RW, 0, NULL, 0 },
+    { "AFSR0_EL2", 0,5,1, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL2_RW, 0, NULL, 0 },
+    { "AFSR1_EL2", 0,5,1, 3,4,1, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL2_RW, 0, NULL, 0 },
     { "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
       PL2_RW, 0, NULL, 0 },
     { "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
@@ -2563,6 +2567,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
     { "HMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
       PL2_RW, 0, NULL, 0 },
+    { "AFSR0_EL2", 0,5,1, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL2_RW, 0, NULL, 0 },
+    { "AFSR1_EL2", 0,5,1, 3,4,1, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL2_RW, 0, NULL, 0 },
     { "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
       PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0},
       NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
@@ -2658,6 +2666,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[3]) },
     { "AMAIR_EL3", 0,10,3, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_CONST,
       PL3_RW, 0, NULL, 0 },
+    { "AFSR0_EL3", 0,5,1, 3,6,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL3_RW, 0, NULL, 0 },
+    { "AFSR1_EL3", 0,5,1, 3,6,1, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+      PL3_RW, 0, NULL, 0 },
     REGINFO_SENTINEL
 };