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https://github.com/yuzu-emu/unicorn.git
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target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)
Add emulation of nanoMIPS instructions situated in pool p_lsx, and emulation of LSA instruction as well. Backports commit eac5266459fb83e70fbf33f95c7c846f89df5c6a from qemu
This commit is contained in:
Yongbok Kim
Lioncash
parent
db0ca1924e
commit
e9442a5ca9
@ -17202,17 +17202,17 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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save_cpu_state(ctx, 1);
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gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
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gen_store_gpr(ctx, t0, rt);
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gen_store_gpr(tcg_ctx, t0, rt);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case NM_RDPGPR:
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gen_load_srsgpr(rs, rt);
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gen_load_srsgpr(ctx, rs, rt);
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break;
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case NM_WRPGPR:
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gen_store_srsgpr(rs, rt);
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gen_store_srsgpr(ctx, rs, rt);
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break;
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case NM_WAIT:
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gen_cp0(env, ctx, OPC_WAIT, 0, 0);
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@ -17235,6 +17235,125 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1;
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rs);
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gen_load_gpr(ctx, t1, rt);
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if ((extract32(ctx->opcode, 6, 1)) == 1) {
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/* PP.LSXS instructions require shifting */
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switch (extract32(ctx->opcode, 7, 4)) {
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case NM_LHXS:
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case NM_SHXS:
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case NM_LHUXS:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 1);
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break;
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case NM_LWXS:
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case NM_SWXS:
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case NM_LWC1XS:
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case NM_SWC1XS:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 2);
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break;
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case NM_LDC1XS:
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case NM_SDC1XS:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 3);
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break;
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}
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}
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gen_op_addr_add(ctx, t0, t0, t1);
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switch (extract32(ctx->opcode, 7, 4)) {
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case NM_LBX:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx,
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MO_SB);
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_LHX:
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/*case NM_LHXS:*/
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx,
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MO_TESW);
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_LWX:
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/*case NM_LWXS:*/
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx,
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MO_TESL);
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_LBUX:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx,
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MO_UB);
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_LHUX:
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/*case NM_LHUXS:*/
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx,
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MO_TEUW);
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gen_store_gpr(tcg_ctx, t0, rd);
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break;
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case NM_SBX:
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_8);
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break;
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case NM_SHX:
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/*case NM_SHXS:*/
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_TEUW);
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break;
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case NM_SWX:
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/*case NM_SWXS:*/
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gen_load_gpr(ctx, t1, rd);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx,
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MO_TEUL);
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break;
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case NM_LWC1X:
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/*case NM_LWC1XS:*/
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case NM_LDC1X:
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/*case NM_LDC1XS:*/
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case NM_SWC1X:
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/*case NM_SWC1XS:*/
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case NM_SDC1X:
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/*case NM_SDC1XS:*/
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if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
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check_cp1_enabled(ctx);
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switch (extract32(ctx->opcode, 7, 4)) {
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case NM_LWC1X:
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/*case NM_LWC1XS:*/
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gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
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break;
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case NM_LDC1X:
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/*case NM_LDC1XS:*/
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gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
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break;
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case NM_SWC1X:
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/*case NM_SWC1XS:*/
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gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
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break;
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case NM_SDC1X:
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/*case NM_SDC1XS:*/
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gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
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break;
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}
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} else {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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}
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static void gen_pool32f_nanomips_insn(DisasContext *ctx)
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{
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int rt, rs, rd;
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@ -17539,7 +17658,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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uint16_t insn;
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uint32_t op;
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int rt, rs;
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int rt, rs, rd;
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int offset;
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int imm;
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@ -17548,6 +17667,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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rt = extract32(ctx->opcode, 21, 5);
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rs = extract32(ctx->opcode, 16, 5);
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rd = extract32(ctx->opcode, 11, 5);
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op = extract32(ctx->opcode, 26, 6);
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switch (op) {
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@ -17608,6 +17728,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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break;
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case NM_POOL32A7:
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switch (extract32(ctx->opcode, 3, 3)) {
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case NM_P_LSX:
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gen_p_lsx(ctx, rd, rs, rt);
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break;
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case NM_LSA:
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/* In nanoMIPS, the shift field directly encodes the shift
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* amount, meaning that the supported shift values are in
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* the range 0 to 3 (instead of 1 to 4 in MIPSR6). */
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gen_lsa(ctx, OPC_LSA, rd, rs, rt,
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extract32(ctx->opcode, 9, 2) - 1);
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break;
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case NM_POOL32AXF:
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gen_pool32axf_nanomips_insn(env, ctx);
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break;
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