From ea2fee2d4d513bf3e5ffd91b104828f5bcaad200 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 28 May 2019 19:11:04 -0400 Subject: [PATCH] target/riscv: Add a base 32 and 64 bit CPU At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Backports commit 8903bf6e6d73d03b988b4a8197132de2ad681ff5 from qemu --- qemu/target/riscv/cpu.c | 14 ++++++++++++++ qemu/target/riscv/cpu.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index dc7b642b..4304cd19 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -112,6 +112,12 @@ static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) #if defined(TARGET_RISCV32) +static void riscv_base32_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) +{ + CPURISCVState *env = &RISCV_CPU(uc, obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); +} + static void rv32gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) { CPURISCVState *env = &RISCV_CPU(uc, obj)->env; @@ -143,6 +149,12 @@ static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *op #elif defined(TARGET_RISCV64) +static void riscv_base64_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) +{ + CPURISCVState *env = &RISCV_CPU(uc, obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); +} + static void rv64gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) { CPURISCVState *env = &RISCV_CPU(uc, obj)->env; @@ -366,12 +378,14 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), #elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index 4d0ed9e1..e3967b45 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -50,6 +50,8 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")