From ea716ff2dbd4949568216cc86eb6df79b02e7096 Mon Sep 17 00:00:00 2001
From: Alistair Francis <alistair.francis@wdc.com>
Date: Mon, 8 Mar 2021 15:26:54 -0500
Subject: [PATCH] target/riscv: Add a riscv_cpu_is_32bit() helper function

Backports 51ae0cabc67c418264d5ae28214603aabc88b9b6
---
 qemu/header_gen.py      | 1 +
 qemu/riscv32.h          | 1 +
 qemu/riscv64.h          | 1 +
 qemu/target/riscv/cpu.c | 9 +++++++++
 qemu/target/riscv/cpu.h | 2 ++
 5 files changed, 14 insertions(+)

diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index d2cc478d..93c02627 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -7324,6 +7324,7 @@ riscv_symbols = (
     'riscv_cpu_fp_enabled',
     'riscv_cpu_get_fflags',
     'riscv_cpu_get_phys_page_debug',
+    'riscv_cpu_is_32bit',
     'riscv_cpu_list',
     'riscv_cpu_mmu_index',
     'riscv_cpu_register_types',
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index 01df659c..671bc4bf 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -4760,6 +4760,7 @@
 #define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv32
 #define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv32
 #define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv32
+#define riscv_cpu_is_32bit riscv_cpu_is_32bit_riscv32
 #define riscv_cpu_list riscv_cpu_list_riscv32
 #define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv32
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 2ad4ef58..70336c6f 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -4760,6 +4760,7 @@
 #define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv64
 #define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv64
 #define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64
+#define riscv_cpu_is_32bit riscv_cpu_is_32bit_riscv64
 #define riscv_cpu_list riscv_cpu_list_riscv64
 #define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv64
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv64
diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index 200b7039..cd08192f 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -88,6 +88,15 @@ const char * const riscv_intr_names[] = {
     "reserved"
 };
 
+bool riscv_cpu_is_32bit(CPURISCVState *env)
+{
+    if (env->misa & RV64) {
+        return false;
+    }
+
+    return true;
+}
+
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 8324ec56..aef42a07 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -386,6 +386,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 9, 1)
 
+bool riscv_cpu_is_32bit(CPURISCVState *env);
+
 /*
  * A simplification for VLMAX
  * = (1 << LMUL) * VLEN / (8 * (1 << SEW))