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target-arm: Use tcg_gen_extrh_i64_i32

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Usually, eliminate an operation from the translator by combining
a shift with an extract.

In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
merely a non-zero value. Given that we can extract both halves of a
64-bit input in one call, this simplifies the code.

Backports commit 7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6 from qemu
This commit is contained in:
Richard Henderson 2018-02-11 01:45:32 -05:00 committed by Lioncash
parent b94da3fc13
commit eb5ed2a844
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 9 additions and 25 deletions
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34
qemu/target-arm/translate-a64.c
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@ -528,13 +528,8 @@ static TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx)
*/
static inline void gen_set_NZ64(TCGContext *tcg_ctx, TCGv_i64 result)
{
TCGv_i64 flag = tcg_temp_new_i64(tcg_ctx);
tcg_gen_setcondi_i64(tcg_ctx, TCG_COND_NE, flag, result, 0);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, flag);
tcg_gen_shri_i64(tcg_ctx, flag, result, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_NF, flag);
tcg_temp_free_i64(tcg_ctx, flag);
tcg_gen_extr_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF, result);
tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF);
}
/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
@ -544,7 +539,7 @@ static inline void gen_logic_CC(TCGContext *tcg_ctx, int sf, TCGv_i64 result)
gen_set_NZ64(tcg_ctx, result);
} else {
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, result);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_NF, result);
tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_ZF);
}
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CF, 0);
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_VF, 0);
@ -571,8 +566,7 @@ static void gen_add_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1);
tcg_gen_andc_i64(tcg_ctx, flag, flag, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
tcg_gen_shri_i64(tcg_ctx, flag, flag, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, flag);
tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, flag);
tcg_gen_mov_i64(tcg_ctx, dest, result);
tcg_temp_free_i64(tcg_ctx, result);
@ -621,8 +615,7 @@ static void gen_sub_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1);
tcg_gen_and_i64(tcg_ctx, flag, flag, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
tcg_gen_shri_i64(tcg_ctx, flag, flag, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, flag);
tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, flag);
tcg_gen_mov_i64(tcg_ctx, dest, result);
tcg_temp_free_i64(tcg_ctx, flag);
tcg_temp_free_i64(tcg_ctx, result);
@ -683,8 +676,7 @@ static void gen_adc_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
tcg_gen_xor_i64(tcg_ctx, vf_64, result, t0);
tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1);
tcg_gen_andc_i64(tcg_ctx, vf_64, vf_64, tmp);
tcg_gen_shri_i64(tcg_ctx, vf_64, vf_64, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, vf_64);
tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_VF, vf_64);
tcg_gen_mov_i64(tcg_ctx, dest, result);
@ -7833,10 +7825,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
} else {
TCGv_i32 tcg_lo = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_hi = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_lo, tcg_op);
tcg_gen_extr_i64_i32(tcg_ctx, tcg_lo, tcg_hi, tcg_op);
gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_lo, tcg_lo, tcg_ctx->cpu_env);
tcg_gen_shri_i64(tcg_ctx, tcg_op, tcg_op, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_hi, tcg_op);
gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_hi, tcg_hi, tcg_ctx->cpu_env);
tcg_gen_deposit_i32(tcg_ctx, tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
tcg_temp_free_i32(tcg_ctx, tcg_lo);
@ -8750,16 +8740,10 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
}
}
static void do_narrow_high_u32(TCGContext *tcg_ctx, TCGv_i32 res, TCGv_i64 in)
{
tcg_gen_shri_i64(tcg_ctx, in, in, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, res, in);
}
static void do_narrow_round_high_u32(TCGContext *tcg_ctx, TCGv_i32 res, TCGv_i64 in)
{
tcg_gen_addi_i64(tcg_ctx, in, in, 1U << 31);
do_narrow_high_u32(tcg_ctx, res, in);
tcg_gen_extrh_i64_i32(tcg_ctx, res, in);
}
static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
@ -8779,7 +8763,7 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
gen_helper_neon_narrow_round_high_u8 },
{ gen_helper_neon_narrow_high_u16,
gen_helper_neon_narrow_round_high_u16 },
{ do_narrow_high_u32, do_narrow_round_high_u32 },
{ tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
};
NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];