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target-i386: Check CR4[DE] for processing DR4/DR5

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Introduce helper_get_dr so that we don't have to put CR4[DE]
into the scarce HFLAGS resource. At the same time, rename
helper_movl_drN_T0 to helper_set_dr and set the helper flags.

Backports commit d0052339236072bbf08c1d600c0906126b1ab258 from qemu
This commit is contained in:
Richard Henderson 2018-02-16 16:27:51 -05:00 committed by Lioncash
parent c6bfe2a03d
commit fcc9dbc103
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
4 changed files with 50 additions and 11 deletions
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46
qemu/target-i386/bpt_helper.c
View File

@ -241,10 +241,11 @@ void helper_single_step(CPUX86State *env)
raise_exception(env, EXCP01_DB);
}
void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY
if (reg < 4) {
switch (reg) {
case 0: case 1: case 2: case 3:
if (hw_breakpoint_enabled(env->dr[7], reg)
&& hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
hw_breakpoint_remove(env, reg);
@ -253,14 +254,49 @@ void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
} else {
env->dr[reg] = t0;
}
} else if (reg == 7) {
return;
case 4:
if (env->cr[4] & CR4_DE_MASK) {
break;
}
/* fallthru */
case 6:
env->dr[6] = t0;
return;
case 5:
if (env->cr[4] & CR4_DE_MASK) {
break;
}
/* fallthru */
case 7:
cpu_x86_update_dr7(env, t0);
} else {
env->dr[reg] = t0;
return;
}
raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
#endif
}
target_ulong helper_get_dr(CPUX86State *env, int reg)
{
switch (reg) {
case 0: case 1: case 2: case 3: case 6: case 7:
return env->dr[reg];
case 4:
if (env->cr[4] & CR4_DE_MASK) {
break;
} else {
return env->dr[6];
}
case 5:
if (env->cr[4] & CR4_DE_MASK) {
break;
} else {
return env->dr[7];
}
}
raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
}
/* Check if Port I/O is trapped by a breakpoint. */
void helper_bpt_io(CPUX86State *env, uint32_t port,
uint32_t size, target_ulong next_eip)

2
qemu/target-i386/cpu.h
View File

@ -922,7 +922,7 @@ typedef struct CPUX86State {
int error_code;
int exception_is_int;
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers */
target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
union {
struct CPUBreakpoint *cpu_breakpoint[4];
struct CPUWatchpoint *cpu_watchpoint[4];

3
qemu/target-i386/helper.h
View File

@ -42,7 +42,8 @@ DEF_HELPER_2(read_crN, tl, env, int)
DEF_HELPER_3(write_crN, void, env, int, tl)
DEF_HELPER_2(lmsw, void, env, tl)
DEF_HELPER_1(clts, void, env)
DEF_HELPER_3(movl_drN_T0, void, env, int, tl)
DEF_HELPER_FLAGS_3(set_dr, TCG_CALL_NO_WG, void, env, int, tl)
DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int)
DEF_HELPER_2(invlpg, void, env, tl)
DEF_HELPER_4(enter_level, void, env, int, int, tl)

10
qemu/target-i386/translate.c
View File

@ -8284,18 +8284,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_64;
else
ot = MO_32;
/* XXX: do it dynamically with CR4.DE bit */
if (reg == 4 || reg == 5 || reg >= 8)
if (reg >= 8) {
goto illegal_op;
}
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm);
gen_helper_movl_drN_T0(tcg_ctx, cpu_env, tcg_const_i32(tcg_ctx, reg), *cpu_T[0]);
tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg);
gen_helper_set_dr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32, *cpu_T[0]);
gen_jmp_im(s, s->pc - s->cs_base);
gen_eob(s);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
tcg_gen_ld_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg);
gen_helper_get_dr(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, cpu_tmp2_i32);
gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]);
}
}