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target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes

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The TCR_EL2 and TCR_EL3 regdefs were incorrectly using the
vmsa_tcr_el1_write function for writes. Since these registers don't
have the A1 bit that TCR_EL1 does, we don't need to do a tlb_flush()
when they are written. Remove the unnecessary .writefn and also the
harmless but unneeded .raw_writefn and .resetfn definitions.

Backports commit 6459b94c26dd666badb3547fef1456992a08e60b from qemu
This commit is contained in:
Peter Maydell 2018-02-23 20:09:08 -05:00 committed by Lioncash
parent eb79db28d5
commit fe2000aa32
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 2 deletions
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10
qemu/target-arm/helper.c
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@ -3126,7 +3126,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
PL2_RW, 0, NULL, 0 },
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
/* no .writefn needed as this can't cause an ASID change;
* no .raw_writefn or .resetfn needed as we never use mask/base_mask
*/
NULL, NULL, NULL, NULL, NULL, NULL },
{ "VTCR", 15,2,1, 0,4,2, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vtcr_el2), {0, 0},
access_el3_aa32ns },
@ -3269,7 +3272,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
NULL, NULL, vmsa_ttbr_write },
{ "TCR_EL3", 0,2,0, 3,6,2, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[3]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
/* no .writefn needed as this can't cause an ASID change;
* no .raw_writefn or .resetfn needed as we never use mask/base_mask
*/
NULL, NULL, NULL, NULL, NULL, NULL },
{ "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[3]) },
{ "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64, 0,