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0273e6ae18
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474 Commits

Author SHA1 Message Date
Lioncash
0273e6ae18
tcg: Put opcodes in a linked list 
The previous setup required ops and args to be completely sequential,
and was error prone when it came to both iteration and optimization.
 2018-02-09 12:54:05 -05:00
Richard Henderson
a41b9acc0c
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full 
The method by which we count the number of ops emitted
is going to change. Abstract that away into some inlines.

Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.
 2018-02-09 09:31:17 -05:00
Richard Henderson
78378289e3
tcg: Move emit of INDEX_op_end into gen_tb_end 
Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu
 2018-02-09 08:51:01 -05:00
Richard Henderson
4d46959c3b
tcg: Reduce ifdefs in tcg-op.c 
Almost completely eliminates the ifdefs in this file, improving
confidence in the lesser used 32-bit builds.

Backports commit 3a13c3f34ce2058e0c2decc3b0f9f56be24c9400 from qemu
 2018-02-09 08:35:52 -05:00
Richard Henderson
500c546444
tcg: Move some opcode generation functions out of line 
Some of these functions are really quite large.  We have a number of
things that ought to be circularly dependent, but we duplicated code
to break that chain for the inlines.

This saved 25% of the code size of one of the translators I examined.
 2018-02-09 08:10:00 -05:00
Richard Henderson
cb7b19ad26
tcg: Change ts->mem_reg to ts->mem_base 
Chain the temporaries together via pointers intstead of indices.
The mem_reg value is now mem_base->reg.  This will be important later.

This does require that the frame pointer have a global temporary
allocated for it.  This is simple bar the existing reserved_regs check.

Backports commit b3a62939561e07bc34493444fa926b6137cba4e8 from qemu
 2018-02-08 13:04:48 -05:00
Richard Henderson
6b4b493dae
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr 
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.

Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu
 2018-02-08 12:33:33 -05:00
Richard Henderson
afb67fc002
target/arm: Fix aa64 ldp register writeback 
Backports commit 3e4d91b94ce400326fae0850578d9e9f30a71adb from qemu
 2018-02-08 08:29:51 -05:00
Eric Blake
37cdcbf771
maint: Fix macros with broken 'do/while(0); ' usage 2018-02-07 20:27:37 -05:00
Lioncash
0f453b0595
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers 
Backports commit 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 from qemu
 2018-02-07 10:09:26 -05:00
Lioncash
dd577f5ea5
target/arm: Change the type of vfp.regs 
Backports commit 3f68b8a5a6862f856524bb347bf348ae364dd43c from qemu
 2018-02-07 09:57:43 -05:00
Lioncash
ef07c136b6
target/arm: Add fp16 support to vfp_expand_imm 
Backports commit 8081796a75414f9ed5ec3d97158e543ed45908ec from qemu.
 2018-02-07 09:47:04 -05:00
Lioncash
b55f35ba92
target/arm: Split out vfp_expand_imm 
Backports commit e90a99fe6bde9b85bff8c052ade51520f20d9bce from qemu.
 2018-02-07 09:44:52 -05:00
Lioncash
4c165ed788
translate-a64: Silence unused variable warning 2018-02-06 08:38:01 -05:00
Merry
29d38d7c22
Merge pull request #10 from lioncash/el-busto-ldst-exclusive 
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
 2018-02-05 20:59:25 +00:00
Merry
b7bb608197
Merge pull request #9 from lioncash/ia64 
tcg: Drop ia64 host support
 2018-02-05 20:59:18 +00:00
Merry
82c4212ce3
Merge pull request #8 from lioncash/optimize 
Backport REV16 optimizations from qemu
 2018-02-05 20:58:58 +00:00
Lioncash
1e451b386a
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks 
Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu
 2018-02-04 23:17:45 -05:00
Lioncash
7f665d8c1e
tcg: Drop ia64 host support 
Backports commit a46c1244a0d65d5f37fc12e4d42f2479eac87b52 from qemu
 2018-02-04 18:33:02 -05:00
Lioncash
5a37b8c28e
Backport optimizations to AArch32's REV16 handling 
Backports commit 68cedf733ae32363ccf54f0b52c8a424d5ec98ed from qemu
 2018-02-04 14:53:28 -05:00
Lioncash
4a8a92bad2
Backport optimizations to AArch64's REV16 handling 
Backports commits abb1066df313602ef0ca631126bd342d399d5359 and e4256c3cbf7eefebc0bc6e1f472c47c6dd20b996 from qemu.
 2018-02-04 14:45:39 -05:00
Lioncash
122d54e23e
Backport the SVE feature flag 
Backports commit 0d0a16c647650d476219a5e1313dec434f9fbebb in qemu to unicorn
 2018-02-02 08:52:15 -05:00
Lioncash
4fb2fbfacf
Backport the JAZELLE feature flag 
Backports commit c99a55d38dd5b5131f3fcbbaf41828a09ee62544 in qemu to unicorn
 2018-02-02 08:50:18 -05:00
Lioncash
84319130cd
Backport the M_SECURITY feature flag 
Backports relevant parts from commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f in qemu to unicorn
 2018-02-02 08:44:46 -05:00
Lioncash
20038fb801
Backport the PMU feature flag 
Backports the applicable code from commit 929e754d5a621cd53f30e69b766ccf381b58d124 to unicorn
 2018-02-02 08:28:27 -05:00
Lioncash
35100ce4e0
Backport the VBAR feature flag 
Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
 2018-02-02 08:24:12 -05:00
Lioncash
291b5753eb
Backport the THUMB_DSP feature flag 
Backports commit 62b44f059a84d1ac580a653fc4110dfabaef6b83 in qemu to unicorn.
 2018-02-02 07:59:26 -05:00
Lioncash
438e2836e0
helper_a64: Fix CRC32's implementation 2018-01-29 09:24:36 -05:00
Lioncash
d41b200fd4
A64: Add EOR3 and BCAX support 
Backported to unicorn from: https://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05003.html
 2018-01-25 21:18:36 -05:00
MerryMage
4128f3b259 aarch64: Add FPCR and FPSR registers 2018-01-16 17:37:47 +00:00
MerryMage
f90c819a33 aarch64: Add pstate pseudoregister 2018-01-16 17:37:17 +00:00
bunnei
73f4573535 aarch64: Add exception syndrome pseudo register. 2018-01-03 19:41:12 -05:00
Nguyen Anh Quynh
d5f83a9c2e arm: cleanup for ARM_CPU 2017-12-21 09:43:33 +08:00
Nguyen Anh Quynh
e67be36c88 arm: remove unused variable in arm_cpu_get_phys_page_debug() 2017-12-20 22:12:35 +08:00
Nguyen Anh Quynh
3e0d0cfab7 i386: fix signed int overflow in #923 & #924 2017-12-16 10:28:45 +08:00
Andrew Dutcher
d7735487f7 Use the qemu helpers to get/set the x86 eflags (#878) 2017-09-15 22:18:38 +07:00
Andrew Dutcher
363cbacee4 Only set eip to the instruction pointer after an interrupt if the interrupt was user-generated (#875) 2017-08-29 17:14:36 +07:00
darkf
42d0632108 Fix typo in ARM tcg-target.c (#859) 2017-07-22 23:36:38 +08:00
vardyh
ad767abda8 x86::trans: handle illegal case for opc c6/c7 
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Signed-off-by: vardyh <vardyh.dev@gmail.com>
 2017-05-25 15:22:45 +08:00
misson20000
014ccfb94a Aarch64 add thread registers (#834) 
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
 2017-05-14 14:42:49 +07:00
bulaza
4b9efdc986 Adding INSN hook checks for x86 (#833) 
* adding INSN hook checking for x86

* tabs to spaces

* need to return bool not uc_err

* fixed conditional after switching to bool
 2017-05-14 00:16:17 +07:00
Ryan Hileman
ae6ea3b91d fix arm64 hang (fix #827) (#828) 2017-05-09 20:19:32 +08:00
Samuel Groß
5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
zhangwm
4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816) 
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
 2017-05-04 20:00:48 +08:00
Ryan Hileman
1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Ryan Hileman
187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
zhangwm
2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh
513075e061 arm: fix an warning reported by GCC 2017-04-21 21:12:57 +08:00
Nguyen Anh Quynh
e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
0xSeb
605400e10e determine correct Thumb/Thumb2 instruction size (16/32-bit) for code … (#796) 
* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook
 2017-04-15 00:39:56 +08:00