301 Commits

Author	SHA1	Message	Date
Aleksandar Markovic	462d062240	target/mips: Clean up handling of CP0 register 19 ... Clean up handling of CP0 register 19. Backports commit be274dc18ee3682bb3a2ba7e5ccd3061b103cbec from qemu	2019-11-18 23:22:07 -05:00
Aleksandar Markovic	e126751cdc	target/mips: Clean up handling of CP0 register 18 ... Clean up handling of CP0 register 18. Backports commit e8dcfe825a51c5e963813343ec4112f06a0acf68 from qemu	2019-11-18 23:21:19 -05:00
Aleksandar Markovic	0424d7bd24	target/mips: Clean up handling of CP0 register 17 ... Clean up handling of CP0 register 17. Backports commit 706ce142056b1304ea21db53b73d128295771a71 from qemu	2019-11-18 23:18:16 -05:00
Aleksandar Markovic	04de1c3a5e	target/mips: Clean up handling of CP0 register 16 ... Clean up handling of CP0 register 16. Backports commit 433efb4cca1d942b6849be953ea166b492e9bb59 from qemu	2019-11-18 23:14:41 -05:00
Aleksandar Markovic	e54d2617a1	target/mips: Clean up handling of CP0 register 15 ... Clean up handling of CP0 register 15. Backports commit 4466cd49e53d3a4418a0f27ea9ff335fd9aed180 from qemu	2019-11-18 23:11:46 -05:00
Aleksandar Markovic	41133450de	target/mips: Clean up handling of CP0 register 14 ... Clean up handling of CP0 register 14. Backports commit 35e4b54d90b07736d24d736c50f236231cde929f from qemu	2019-11-18 23:10:19 -05:00
Aleksandar Markovic	dc1e7c4467	target/mips: Clean up handling of CP0 register 13 ... Clean up handling of CP0 register 13. Backports commit e3c7559d8902fbb9857fb94fc5391f258cc3c4d1 from qemu	2019-11-18 23:08:20 -05:00
Aleksandar Markovic	3f76658fd8	target/mips: Clean up handling of CP0 register 12 ... Clean up handling of CP0 register 12. Backports commit 2b0848674b4143bf5b2b6f7de6b8587dd52c31dd from qemu	2019-11-18 23:06:38 -05:00
Aleksandar Markovic	5812937c52	target/mips: Clean up handling of CP0 register 11 ... Clean up handling of CP0 register 11. Backports commit f5f3834ff0f7d237fa9d5c67544ae5f5d49eaaf7 from qemu	2019-11-18 23:04:18 -05:00
Aleksandar Markovic	16e817b003	target/mips: Clean up handling of CP0 register 10 ... Clean up handling of CP0 register 10. Backports commit 860ffef0477a92f1944f10528887fa5e74e6535d from qemu	2019-11-18 23:03:25 -05:00
Aleksandar Markovic	11d02fc0b7	target/mips: Clean up handling of CP0 register 9 ... Clean up handling of CP0 register 9. Backports commit e5a98a7232e10632032be8f896ce0aaf171b6fd5 from qemu	2019-11-18 23:01:54 -05:00
Aleksandar Markovic	f4015517ab	target/mips: Clean up handling of CP0 register 8 ... Clean up handling of CP0 register 8. Backports commit 67d167d2d83d059932c99c077b402b94339c8cf0 from qemu	2019-11-18 22:59:32 -05:00
Aleksandar Markovic	38f0e31950	target/mips: Clean up handling of CP0 register 7 ... Clean up handling of CP0 register 7. Backports commit 143a9875e51a358924154ffa76135ca29415dfb5 from qemu	2019-11-18 22:55:22 -05:00
Aleksandar Markovic	95fa7aae61	target/mips: Clean up handling of CP0 register 6 ... Clean up handling of CP0 register 6. Backports commit 9023594b4081585518faf9b144bce62067381990 from qemu	2019-11-18 22:54:26 -05:00
Aleksandar Markovic	49eeba113e	target/mips: Clean up handling of CP0 register 5 ... Clean up handling of CP0 register 5. Backports commit a1e76353e389f93e63bf1175c8422e5e7759662e from qemu	2019-11-18 22:51:19 -05:00
Aleksandar Markovic	11ac98331a	target/mips: Clean up handling of CP0 register 4 ... Clean up handling of CP0 register 4. Backports commit 020fe379093deb116d72174268335d60133f0e26 from qemu	2019-11-18 22:46:46 -05:00
Aleksandar Markovic	d96b3d06c4	target/mips: Clean up handling of CP0 register 3 ... Clean up handling of CP0 register 3. Backports commit acd3731632c5737eaeb230d76fd55ce871a33439 from qemu	2019-11-18 22:42:17 -05:00
Aleksandar Markovic	8644845898	target/mips: Clean up handling of CP0 register 2 ... Clean up handling of CP0 register 2. Backports commit 6d27d5bd73489a0560a6613e2b5633e221999db9 from qemu	2019-11-18 22:38:46 -05:00
Aleksandar Markovic	9450b71a13	target/mips: Clean up handling of CP0 register 1 ... Clean up handling of CP0 register 1 Backports commit 30deb4605bf0bb4cc0682216002dfed738bd5700 from qemu	2019-11-18 22:33:29 -05:00
Aleksandar Markovic	47adeabf87	target/mips: Clean up handling of CP0 register 0 ... Clean up handling of CP0 register 0. Backports commit 1b142da5f82a8fcdc7783a418592de654d5c6052 from qemu	2019-11-18 22:25:31 -05:00
tony.nguyen@bt.com	b4c2c94602	configure: Define target access alignment in configure ... This patch moves the define of target access alignment earlier from target/foo/cpu.h to configure. Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now accelerator independent MemOp" Backports commit 52bf9771fdfce98e98cea36a17a18915be6f6b7f from qemu	2019-11-18 21:41:35 -05:00
Aleksandar Markovic	551b3db088	target/mips: Style improvements in translate.c ... Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Backports commit 71375b59241a27b75d287b9216e5e82e43d763d8 from qemu	2019-11-18 21:36:30 -05:00
Aleksandar Markovic	cf6adb51e0	target/mips: Style improvements in cpu.c ... Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Backports commit cf02a1164815ed6682c21070ddc95b88c31ff476 from qemu	2019-11-18 21:25:54 -05:00
Aleksandar Markovic	780b748780	target/mips: Style improvements in cp0_timer.c ... Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Backports commit 2f0d0196721d207297ce00a6cb39fc52005ccc7a from qemu	2019-11-18 21:24:37 -05:00
Alex Bennée	3afb3723c7	target/mips: rationalise softfloat includes ... We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h in cpu.h for the few bits that are global. We also move the restore_snan_bit_mode into internal.h and include -helpers.h there. Backports commit 502700d0674919309a19bfd016ea0680c6b7747d from qemu	2019-11-18 21:15:19 -05:00
kj.xwings.l	038b4f3345	Removed hardcoded CP0C3_ULRI (#1098) ... * activate CP0C3_ULRI for CONFIG3, mips * updated with mips patches * updated with mips patches * remove hardcoded config3 * git ignore vscode * fix spacing issue and turn on floating point Backports most of commit 24f55a7973278f20f0de21b904851d99d4716263 from unicorn. Ignores internal core modifications, as this would be special-casing non-upstreamed behavior.	2019-08-08 20:08:57 -04:00
Aleksandar Markovic	e2bc3161b4	target/mips: Fix emulation of MSA pack instructions on big endian hosts ... Fix emulation of MSA pack instructions on big endian hosts. Backports commit 51229582583a4b64e93f2655153d905e4d8583d2 from qemu	2019-08-08 19:51:34 -04:00
Aleksandar Markovic	812f3e4fed	target/mips: Add 'fall through' comments for handling nanoMips' SHXS, SWXS ... This was found by GCC 8.3 static analysis. Missed in commit fb32f8c8560. Backports commit 45152d050213a1221a5a900283976454bf6308bf from qemu	2019-08-08 19:45:25 -04:00
Aleksandar Markovic	572c95e709	target/mips: Add missing 'break' for certain cases of MTTR handling ... This was found by GCC 8.3 static analysis. Fixes: ead9360e2fb Backports commit 0d0304f2c4967c892a3216638fc4cb078afa2b44 from qemu	2019-08-08 19:38:18 -04:00
Aleksandar Markovic	720aff63da	target/mips: Add missing 'break' for certain cases of MFTR handling ... This was found by GCC 8.3 static analysis. Fixes: ead9360e2fb Backports commit f1fadbb27af04115c9d24e0902d88a38d0266854 from qemu	2019-08-08 19:37:34 -04:00
Aleksandar Markovic	b2aa75be33	target/mips: Add missing 'break' for a case of MTHC0 handling ... This was found by GCC 8.3 static analysis. Fixes: 5fb2dcd1792 Backports commit ab8c34105a0ddd0c05159fb76919a18de8df4e8f from qemu	2019-08-08 19:36:39 -04:00
Aleksandar Markovic	1e148beb0e	target/mips: Correct helper for MSA FCLASS.<W|D> instructions ... Correct helper for MSA FCLASS.<W|D> instructions. Backports commit 698c5752c4e618dc17b4c78dfa566896c7bce5ef from qemu	2019-08-08 16:30:15 -04:00
Aleksandar Markovic	bf194f980c	target/mips: Unroll loops for MSA float max/min instructions ... Slight preformance improvement for MSA float max/min instructions. Backports commit 807e6773a5eba62054843b13d96ff778b90aba09 from qemu	2019-08-08 16:28:49 -04:00
Aleksandar Markovic	dd747162e5	target/mips: Correct comments in msa_helper.c ... Fix some errors in comments for MSA helpers. Backports commit 44da090ba02e60515aa0dc72b30ecc6f56aea771 from qemu	2019-08-08 16:24:47 -04:00
Aleksandar Markovic	87edd2a82a	target/mips: Correct comments in translate.c ... Fix some checkpatch comment-related warnings. Backports commit 7480515fcc1b0f7119953d89e93b8507127aeb62 from qemu	2019-08-08 16:23:02 -04:00
Aleksandar Markovic	977e53b921	target/mips: Fix emulation of ILVR.<B|H|W> on big endian host ... Fix emulation of ILVR.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Backports commit 14f5d874bcd533054648bb7cc767c7169eaf2f1c from qemu	2019-06-30 20:03:23 -04:00
Aleksandar Markovic	f7fc20c9ee	target/mips: Fix emulation of ILVL.<B|H|W> on big endian host ... Fix emulation of ILVL.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Backports commit 8e74bceb00120b23f0931e4e4478d1b10e0970d4 from qemu	2019-06-30 20:02:12 -04:00
Aleksandar Markovic	929bd90968	target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host ... Fix emulation of ILVOD.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Backports commit b000169e4ed44a3925b6fd22fa0dd6e22bb02b81 from qemu	2019-06-30 19:54:35 -04:00
Aleksandar Markovic	17dd65b771	target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host ... Fix emulation of ILVEV.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Backports commit 98880cb5a669a35b5bc75432027f2b9fff566aea from qemu	2019-06-30 19:52:14 -04:00
Aleksandar Markovic	e9dc22c280	target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c ... Remove if-else-switch-case-arms-related checkpatch errors. Backports commit 1f8929d241c5461f3e98d52f54bcdadd35554448 from qemu	2019-06-30 19:42:16 -04:00
Aleksandar Markovic	1e52cb8fa1	target/mips: Fix some space checkpatch errors in translate.c ... Remove some space-related checkpatch warning. Backports commit 235785e8347558f36be21aa99efa1ba517ecc827 from qemu	2019-06-30 19:34:41 -04:00
Richard Henderson	8f53f09a05	cpu: Introduce CPUNegativeOffsetState ... Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Backports commit 5b146dc716cfd247f99556c04e6e46fbd67565a0 from qemu	2019-06-13 15:08:25 -04:00
Richard Henderson	a672b89e3b	cpu: Introduce cpu_set_cpustate_pointers ... Consolidate some boilerplate from foo_cpu_initfn. Backports commit 7506ed902eb97fe4e2a1dd16766c621d32ecc40d from qemu	2019-06-12 12:27:16 -04:00
Richard Henderson	ac176ccb38	cpu: Move ENV_OFFSET to exec/gen-icount.h ... Now that we have ArchCPU, we can define this generically, in the one place that needs it. Backports commit 677c4d69ac21961e76a386f9bfc892a44923acc0 from qemu	2019-06-12 12:20:21 -04:00
Richard Henderson	5790c1648d	target/mips: Use env_cpu, env_archcpu ... Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 5a7330b35cabc9e2fd3a8577b7004b63af8c57f3 from qemu	2019-06-12 11:55:43 -04:00
Richard Henderson	fbf91a6535	cpu: Replace ENV_GET_CPU with env_cpu ... Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Backports commit 29a0af618ddd21f55df5753c3e16b0625f534b3c from qemu	2019-06-12 11:16:16 -04:00
Richard Henderson	ae94fb5992	cpu: Define ArchCPU ... For all targets, do this just before including exec/cpu-all.h. Backports commit 2161a612b4e1d388046320bc464adefd6bba01a0 from qemu	2019-06-12 11:08:39 -04:00
Richard Henderson	e3f1f25996	cpu: Define CPUArchState with typedef ... For all targets, do this just before including exec/cpu-all.h. Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu	2019-06-12 11:06:36 -04:00
Richard Henderson	df2a890bd7	tcg: Split out target/arch/cpu-param.h ... For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Backports commit 74433bf083b0766aba81534f92de13194f23ff3e from qemu	2019-06-10 19:35:46 -04:00
Aleksandar Markovic	93473b2e09	target/mips: Unroll loops in helpers for MSA logic instructions ... Unroll loops in helpers for MSA logic instructions for better performance. Backports commit 5d161bc81877327bc0b2a6d8974e07ffdc6881a5 from qemu	2019-06-10 13:56:04 -04:00