3 Commits

Author	SHA1	Message	Date
Richard Henderson	e98c731550	target/riscv: Convert to CPUClass::tlb_fill ... Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu	2019-05-16 17:24:01 -04:00
Alistair Francis	a9cc62cb23	target/riscv: Remove unused struct ... Backports commit 6b745d4fada5c73db44f596a62e29a5dbe3fc53f from qemu	2019-03-19 23:58:31 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00