5 Commits

Author	SHA1	Message	Date
Alex Bennée	a02b9b81a9	arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 ... Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0	2018-03-08 15:42:48 -05:00
Alex Bennée	ba8df54753	arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 ... These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu	2018-03-08 12:59:37 -05:00
Alex Bennée	4a6a41d2c5	arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 ... The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu	2018-03-08 12:56:15 -05:00
Alex Bennée	af75074fe7	arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) ... This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu	2018-03-08 12:49:30 -05:00
Thomas Huth	b2f1326437	Move target-* CPU file into a target/ folder ... We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu	2018-03-01 22:50:58 -05:00