5 Commits

Author	SHA1	Message	Date
Kito Cheng	5a7ad783e9	target/riscv: Fix wrong expanding for c.fswsp ... base register is no rs1 not rs2 for fsw. Backports commit 620455350a8da7cc62ae82cb69dd5c556f744136 from qemu	2019-03-26 20:39:34 -04:00
Bastian Koppelmann	c0f036578c	target/riscv: Fix manually parsed 16 bit insn ... during the refactor to decodetree we removed the manual decoding that is necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld and c.fsw/c.sd. This reintroduces the manual parsing and the omited implementation. Backports commit f330433b3633647b047cfa418c2ca4d18fda69c7 from qemu	2019-03-19 05:44:58 -04:00
Bastian Koppelmann	580457a1d2	target/riscv: Convert quadrant 2 of RVXC insns to decodetree ... Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu	2019-03-19 04:53:07 -04:00
Bastian Koppelmann	b4854e3340	target/riscv: Convert quadrant 1 of RVXC insns to decodetree ... Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu	2019-03-19 04:50:08 -04:00
Lioncash	8d294a7897	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00