Commit Graph

4 Commits

Author SHA1 Message Date
Palmer Dabbelt
fc662c281a
target/riscv: Zero extend the inputs of divuw and remuw
While running the GCC test suite against 4.0.0-rc0, Kito found a
regression introduced by the decodetree conversion that caused divuw and
remuw to sign-extend their inputs. The ISA manual says they are
supposed to be zero extended:

DIVW and DIVUW instructions are only valid for RV64, and divide the
lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as
signed and unsigned integers respectively, placing the 32-bit
quotient in rd, sign-extended to 64 bits. REMW and REMUW
instructions are only valid for RV64, and provide the corresponding
signed and unsigned remainder operations respectively. Both REMW
and REMUW always sign-extend the 32-bit result to 64 bits, including
on a divide by zero.

Here's Kito's reduced test case from the GCC test suite

unsigned calc_mp(unsigned mod)
{
unsigned a,b,c;
c=-1;
a=c/mod;
b=0-a*mod;
if (b > mod) { a += 1; b-=mod; }
return b;
}

int main(int argc, char *argv[])
{
unsigned x = 1234;
unsigned y = calc_mp(x);

if ((sizeof (y) == 4 && y != 680)
|| (sizeof (y) == 2 && y != 134))
abort ();
exit (0);
}

I haven't done any other testing on this, but it does fix the test case.

Backports commit f17e02cd3731bdfe2942d1d0b2a92f26da02408c from qemu
2019-03-26 20:38:17 -04:00
Bastian Koppelmann
1765e6a090
target/riscv: Rename trans_arith to gen_arith
Backports commit 8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3 from qemu
2019-03-19 05:35:44 -04:00
Bastian Koppelmann
28daad082b
target/riscv: Remove manual decoding of RV32/64M insn
Backports commit 1288701682d81b93f62e01cd87001dc90b30b881 from qemu
2019-03-19 05:34:32 -04:00
Bastian Koppelmann
81013f9e2b
target/riscv: Convert RV32A insns to decodetree
Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 16:25:50 -04:00