5 Commits

Author	SHA1	Message	Date
Stefan Markovic	64bec62433	target/mips: Improve DSP R2/R3-related naming ... Do following replacements: ASE_DSPR2 -> ASE_DSP_R2 ASE_DSPR3 -> ASE_DSP_R3 MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2 MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3 check_dspr2() -> check_dsp_r2() check_dspr3() -> check_dsp_r3() and several other similar minor replacements. Backports commit 908f6be1b9cbc270470230f805d6f7474ab3178d from qemu	2018-10-23 13:42:01 -04:00
Stefan Markovic	071fe91d6a	target/mips: Add bit definitions for DSP R3 ASE ... Add DSP R3 ASE related bit definition for insn_flags and hflags. Backports commit 6208f09441dcf8d142ff0e1624ef12da298776a4 from qemu	2018-10-23 13:19:18 -04:00
Philippe Mathieu-Daudé	2a27a61c51	target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) ... Distribute bits 56-63 vendor-specific ASEs as follows: - bits 0-31 MIPS base instruction sets - bits 32-47 MIPS ASEs - bits 48-55 vendor-specific base instruction sets - bits 56-63 vendor-specific ASEs Backports commit 45ebdd24c3de158890ce390df39855a891e80701 from qemu	2018-10-23 13:18:11 -04:00
Aleksandar Markovic	31f42b9f2c	target/mips: Add preprocessor constants for nanoMIPS ... Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants. Backports commit fa7c0c9f5bc12970858a89f46dd5012c01545b80 from qemu	2018-08-27 04:11:21 -04:00
Thomas Huth	b2f1326437	Move target-* CPU file into a target/ folder ... We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu	2018-03-01 22:50:58 -05:00