Commit Graph

1516 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
99f3647d2e Merge pull request #655 from angr/fix/slow_mem_mapping
Remove unmapped/freed memory regions from the object property list.
2016-10-21 00:04:35 +08:00
Fish
ad7ae63e92 Remove unmapped/freed memory regions from the object property list.
This commit fixes the following issues:
- Any unmapped/free'd memory regions (MemoryRegion instances) are not
  removed from the object property linked list of its owner (which is
  always qdev_get_machine(uc)). This issue makes adding new memory
  mapping by calling mem_map() or mem_map_ptr() slower as more and more
  memory pages are mapped and unmapped - yes, even if those memory pages
  are unmapped, they still impact the speed of future memory page
  mappings due to this issue.
- FlatView is not reconstructed after a memory region is freed during
  unmapping, which leads to a use-after-free the next time a new memory
  region is mapped in address_space_update_topology().
2016-10-20 03:48:58 -07:00
Nguyen Anh Quynh
67905ab147 python: rename test_i386_reg_save() to test_i386_context_save() 2016-10-13 20:57:34 +08:00
Nguyen Anh Quynh
756f148038 typo 2016-10-12 11:10:20 +08:00
Nguyen Anh Quynh
b991b71cf5 update CREDITS.TXT 2016-10-12 11:07:11 +08:00
Nguyen Anh Quynh
8f99d20695 turn cpu_context_size() into static function 2016-10-12 11:05:32 +08:00
Andrew Dutcher
bfa51bb5dc rename another saved regs to saved context 2016-10-11 13:07:53 -07:00
Andrew Dutcher
80f35d3b2b remove safety checks, for some reason 2016-10-11 13:07:14 -07:00
Andrew Dutcher
ea54204952 Tweak some names in a few places, encapsulate the uc_context struct to hide it from users for some reason 2016-10-10 14:04:51 -07:00
Andrew Dutcher
1ab2154fe5 Change save/restore API to have explicit alloc/free functions. Python has explicit save/update functions. 2016-10-07 11:39:42 -07:00
Nguyen Anh Quynh
6c54f9ce48 first_cpu is obsolete by recent changes 2016-10-07 10:10:18 +08:00
Nguyen Anh Quynh
a6e8564153 typo 2016-10-07 10:06:53 +08:00
Nguyen Anh Quynh
73577cbcd1 rename uc_regstate_restore to uc_context_restore, uc_context_save to uc_context_save 2016-10-07 10:03:19 +08:00
Nguyen Anh Quynh
b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Nguyen Anh Quynh
1035b406e1 Merge pull request #649 from stephengroat/fix_test
Update test_hang.c
2016-10-06 01:31:55 +08:00
Stephen
0137a66c61 Update test_hang.c 2016-10-05 10:29:16 -07:00
Stephen
f2998f14cd Update test_hang.c 2016-10-05 09:20:36 -07:00
danghvu
fb9cd97504 memleak: Fix m68k memleak 2016-10-03 14:47:03 -05:00
danghvu
84d99412bc memleak: Fix Sparc memory leak 2016-10-03 14:23:27 -05:00
danghvu
6aea0aee58 memleak: Add back object release for uc->cpu 2016-10-03 14:21:47 -05:00
Nguyen Anh Quynh
b7ad7f180c update docs/COMPILE-NIX.md 2016-10-01 00:01:32 +08:00
Nguyen Anh Quynh
7d15a60b25 arm64: disable deadcode introduced by PR #643 2016-09-29 12:34:44 +08:00
Nguyen Anh Quynh
507d557aa5 arm: disable deadcode introduced by PR #643 2016-09-29 12:33:16 +08:00
Andrew Dutcher
e3b0e52013 Rename save/restore functions to match the style of the rest of the API 2016-09-28 21:21:44 -07:00
Ryan Hileman
cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00
Nguyen Anh Quynh
60a7371ec2 Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2016-09-22 08:46:30 +08:00
Nguyen Anh Quynh
d90ec0e74d add link to Perl binding 2016-09-22 08:46:25 +08:00
Nguyen Anh Quynh
8181a5eaf0 Merge pull request #641 from adrianherrera/bugfix/haskell-sample-thumb-fix
Fixed ARM THUMB Haskell sample as per Issue #638
2016-09-21 15:52:29 +08:00
Adrian Herrera
65f1e4d550 [haskell-bindings] Fixed ARM THUMB sample as per issue #638 2016-09-21 09:47:52 +02:00
Nguyen Anh Quynh
fb4dc10fe9 Merge pull request #640 from ret2libc/fix_install3
bindings/python: fix install3
2016-09-20 22:41:16 +08:00
Riccardo Schirone
c16a13495d bindings/python: fix install3 2016-09-20 14:22:38 +00:00
Nguyen Anh Quynh
4188c4cbca Merge branch 'master' into rhelmot-feat/setup_stuff 2016-09-20 21:00:38 +08:00
Nguyen Anh Quynh
95e8dc0fb8 ruby & java: fix address of Thumb sample 2016-09-20 20:16:29 +08:00
Nguyen Anh Quynh
5092bb11f1 Merge pull request #639 from esanfelix/master
Fixed ARM sample to properly run THUMB code #638
2016-09-20 20:07:47 +08:00
esanfelix
7d99b598f1 Fix #638 for python sample too 2016-09-20 10:29:21 +02:00
esanfelix
fce82b9532 Fixed ARM sample to properly run THUMB code #638 2016-09-20 10:15:58 +02:00
Nguyen Anh Quynh
5af4880f1a Merge pull request #637 from lukenels/haskell-fix
Relax transformers constraint for haskell bindings for GHC 8
2016-09-16 23:23:59 +07:00
Luke Nelson
3bc55f9568 Relax transformers constraint for haskell bindings for GHC 8 2016-09-15 19:04:18 -07:00
Andrew Dutcher
ac99b5bd14 Minor tweaks to python setup process; update gitignore 2016-09-12 14:06:50 -07:00
Andrew Dutcher
47af3ca190 Remove PKG-INFO make lines left over from the original capstone skeleton 2016-09-12 14:06:20 -07:00
Andrew Dutcher
edd49cd21c Remove version number from shared library filename packaged with python bindings 2016-09-12 14:06:20 -07:00
Andrew Dutcher
6c042410ae Basically, make python builds work as expected 2016-09-12 14:06:20 -07:00
Andrew Dutcher
20ce432dbc Fix bracket style 2016-09-09 11:55:20 -07:00
Andrew Dutcher
3deb9fdcad Fix save/restore to work while emulation is not active 2016-09-08 14:41:34 -07:00
Andrew Dutcher
885b809004 Add python bindings for reg save/restore 2016-09-08 14:40:39 -07:00
Nguyen Anh Quynh
d59081b073 Merge pull request #630 from 4577/master
Remove BUILDDIR-specific code
2016-09-04 15:30:49 +08:00
4577
1f978de447 Remove BUILDDIR-specific code 2016-09-04 08:59:31 +02:00
Andrew Dutcher
f2af98942b Added (failing?) test for reg save/restore 2016-08-31 20:25:28 -05:00
Nguyen Anh Quynh
d0f30547f8 Merge pull request #628 from rhelmot/fix/self_modifying_instructions
Document assembly instructions for x86_self_modifying
2016-08-31 09:50:35 +08:00
Andrew Dutcher
f8ac51bb3d Document assembly instructions for x86_self_modifying 2016-08-30 14:40:26 -05:00