5 Commits

Author	SHA1	Message	Date
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00
zhangwm	2e973a13f0	arm64eb: add support for ARM64 big endian.	2017-04-24 23:30:01 +08:00
zhangwm	d8fe34a2e8	armeb: Add support for ARM big endian.	2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh	7789a06d2d	cleanup qemu/default-configs/	2017-01-19 14:52:30 +08:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00