Konrad Rzeszutek Wilk 0023d048aa i386: define the AMD 'amd-ssbd' CPUID feature bit ... AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Anyhow, this means that on future AMD CPUs there will be _two_ ways to deal with SSBD. Backports commit a764f3f7197f4d7ad8fe8424269933de912224cb from qemu		2018-07-03 00:24:24 -04:00
..
arm	target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline	2018-06-29 14:15:33 -05:00
i386	i386: define the AMD 'amd-ssbd' CPUID feature bit	2018-07-03 00:24:24 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00