Peter Maydell 04676ed074 target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI ... The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for enabling trapped IEEE floating point exceptions (where IEEE exception conditions cause a CPU exception rather than updating the FPSR status bits). QEMU doesn't implement this (and nor does the hardware we're modelling), but for implementations which don't implement trapped exception handling these control bits are supposed to be RAZ/WI. This allows guest code to test for whether the feature is present by trying to write to the bit and checking whether it sticks. QEMU is incorrectly making these bits read as written. Make them RAZ/WI as the architecture requires. In particular this was causing problems for the NetBSD automatic test suite. Backports commit a15945d98d3a3390c3da344d1b47218e91e49d8b from qemu		2019-02-05 17:45:22 -05:00
..
arm	target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI	2019-02-05 17:45:22 -05:00
i386	i386: Enable NPT and NRIPSAVE for AMD CPUs	2019-02-03 17:55:28 -05:00
m68k	target/m68k: Fix LGPL information in the file headers	2019-02-03 17:55:29 -05:00
mips	target/mips: Add I6500 core configuration	2019-01-25 13:46:18 -05:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00