Yongbok Kim 0597704314 target/mips: Add CP0 PWField register ... Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: MIPS64: BDI (37..32) - Base Directory index GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift MIPS32: GDW (29..24) - Global Directory index UDW (23..18) - Upper Directory index MDW (17..12) - Middle Directory index PTW (11..6 ) - Page Table index PTEW ( 5..0 ) - Page Table Entry shift Backports commit fa75ad1459f4f6abbeb6d375a812dfad61320f58 from qemu		2018-10-23 13:52:31 -04:00
..
arm	sve_helper: Use the QEMU_FLATTEN macro instead of the compiler attribute directly	2018-10-23 13:05:02 -04:00
i386	Initializes i386 prefix value	2018-10-06 04:57:06 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add CP0 PWField register	2018-10-23 13:52:31 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00