unicorn/qemu/target
Peter Maydell 0f0b2e0bd8
target/arm: Honour FPCR.FZ in FRECPX
The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Backports commit 2cfbf36ec07f7cac1aabb3b86f1c95c8a55424ba from qemu
2018-06-02 10:02:57 -04:00
..
arm target/arm: Honour FPCR.FZ in FRECPX 2018-06-02 10:02:57 -04:00
i386 i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639) 2018-05-22 16:58:25 -04:00
m68k tcg: fix s/compliment/complement/ typos 2018-05-22 00:29:51 -04:00
mips target/mips: Remove floatX_maybe_silence_nan from conversions 2018-05-19 23:25:04 -04:00
sparc target/sparc: convert to TranslatorOps 2018-05-11 15:17:12 -04:00