Bastian Koppelmann 177726afb8 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists ... manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu		2019-03-19 05:17:54 -04:00
..
arm	Add ARM MSP, PSP and CONTROL register access (#1071)	2019-03-08 02:24:49 -05:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00