unicorn/qemu/target
Peter Maydell 18bb21c035
target/arm: Honour M-profile FP enable bits
Like AArch64, M-profile floating point has no FPEXC enable
bit to gate floating point; so always set the VFPEN TB flag.

M-profile also has CPACR and NSACR similar to A-profile;
they behave slightly differently:
* the CPACR is banked between Secure and Non-Secure
* if the NSACR forces a trap then this is taken to
the Secure state, not the Non-Secure state

Honour the CPACR and NSACR settings. The NSACR handling
requires us to borrow the exception.target_el field
(usually meaningless for M profile) to distinguish the
NOCP UsageFault taken to Secure state from the more
usual fault taken to the current security state.

Backports commit d87513c0abcbcd856f8e1dee2f2d18903b2c3ea2 from qemu
2019-04-30 10:18:21 -04:00
..
arm target/arm: Honour M-profile FP enable bits 2019-04-30 10:18:21 -04:00
i386 tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
m68k tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
mips tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
riscv tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
sparc tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00