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1b21ced6a1
Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Backports commit 5be2c12337f4cbdbda4efe6ab485350f730faaad from qemu
79 lines
3.9 KiB
Plaintext
79 lines
3.9 KiB
Plaintext
# A32 conditional instructions
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# All of the insn that have a COND field in insn[31:28] are here.
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# All insns that have 0xf in insn[31:28] are in a32-uncond.decode.
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#
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&s_rrr_shi s rd rn rm shim shty
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&s_rrr_shr s rn rd rm rs shty
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# Data-processing (register)
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@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
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&s_rrr_shi
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@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
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&s_rrr_shi rn=0
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@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
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&s_rrr_shi s=1 rd=0
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AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi
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EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi
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SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi
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RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi
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ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi
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ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi
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SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi
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RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi
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TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi
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TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi
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CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi
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CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi
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ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi
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MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
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BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
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MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
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# Data-processing (register-shifted register)
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@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
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&s_rrr_shr
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@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
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&s_rrr_shr rn=0
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@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
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&s_rrr_shr rd=0 s=1
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AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr
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EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr
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SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr
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RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr
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ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr
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ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr
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SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr
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RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr
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TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
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TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
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CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
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CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
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ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr
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MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
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BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr
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MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
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