Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
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cpu_bits.h
cpu_helper.c
cpu_user.h
cpu.c
cpu.h
csr.c
fpu_helper.c
helper.h
instmap.h
Makefile.objs
op_helper.c
pmp.c
pmp.h
translate.c
unicorn.c
unicorn.h