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20c2ed80a2
unicorn/qemu
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Aurelien Jarno 20c2ed80a2
translate-all: fix watchpoints if retranslation not possible 
The tb_check_watchpoint function currently assumes that all memory
access is done either directly through the TCG code or through an
helper which knows its return address. This is obviously wrong as the
helpers use cpu_ldxx/stxx_data functions to access the memory.

Instead of aborting in that case, don't try to retranslate the code, but
assume that the CPU state (and especially the program counter) has been
saved before calling the helper. Then invalidate the TB based on this
address.

Backports commit 8d302e76755b8157373073d7107e31b0b13f80c1 from qemu
2018-02-17 15:22:43 -05:00
..
default-configs arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
docs docs: clarify memory region lifecycle 2018-02-12 15:11:21 -05:00
fpu softfloat: expand out STATUS macro 2018-02-12 13:43:13 -05:00
hw target-i386: disable LINT0 after reset 2018-02-12 21:07:36 -05:00
include softmmu: provide tlb_vaddr_to_host function for user mode 2018-02-17 15:22:43 -05:00
qapi
qobject
qom qom: Fix object_property_add_alias() with [*] 2018-02-12 16:33:58 -05:00
scripts
target-arm target-arm: Correct "preferred return address" for cpreg access exceptions 2018-02-17 15:22:42 -05:00
target-i386 target-i386: create a separate AddressSpace for each CPU 2018-02-13 12:36:26 -05:00
target-m68k unicorn_arm: m68k/translate: Build fixes 2018-02-13 09:15:46 -05:00
target-mips target-mips: enable XPA and LPA features 2018-02-13 14:14:59 -05:00
target-sparc target-*: Increment num_insns immediately after tcg_gen_insn_start 2018-02-11 12:46:30 -05:00
tcg tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS 2018-02-13 08:28:29 -05:00
util bitmap: add atomic test and clear 2018-02-13 10:02:12 -05:00
aarch64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
aarch64eb.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
accel.c
arm.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
armeb.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
CODING_STYLE
configure tcg: Drop ia64 host support 2018-02-04 18:33:02 -05:00
COPYING
COPYING.LIB
cpu-exec.c exec: make iotlb RCU-friendly 2018-02-12 15:20:39 -05:00
cpus.c
cputlb.c memory: replace cpu_physical_memory_reset_dirty() with test-and-clear 2018-02-13 11:25:45 -05:00
exec.c memory: replace cpu_physical_memory_reset_dirty() with test-and-clear 2018-02-13 11:25:45 -05:00
gen_all_header.sh arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
glib_compat.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
HACKING
header_gen.py target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
ioport.c memory: Define API for MemoryRegionOps to take attrs and return status 2018-02-12 17:17:27 -05:00
LICENSE
m68k.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
Makefile
Makefile.objs
Makefile.target tcg: Move some opcode generation functions out of line 2018-02-09 08:10:00 -05:00
memory_mapping.c
memory.c memory: use mr->ram_addr in "is this RAM?" assertions 2018-02-13 11:31:02 -05:00
mips64.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mips64el.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mips.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mipsel.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
powerpc.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h Add MemTxAttrs to the IOTLB 2018-02-12 18:38:38 -05:00
sparc64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
sparc.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
tcg-runtime.c
translate-all.c translate-all: fix watchpoints if retranslation not possible 2018-02-17 15:22:43 -05:00
translate-all.h translate-all: remove unnecessary argument to tb_invalidate_phys_range 2018-02-13 09:04:51 -05:00
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00