James Hogan 22ca920e40 target/mips: Decode MIPS32 EVA load & store instructions ... Implement decoding of MIPS32 EVA loads and stores. These access the user address space from kernel mode when implemented, so for each instruction we need to check that EVA is available from Config5.EVA & check for sufficient COP0 privilege (with the new check_eva()), and then override the mem_idx used for the operation. Unfortunately some Loongson 2E instructions use overlapping encodings, so we must be careful not to prevent those from being decoded when EVA is absent. Backports commit 7696414729b2d0f870c80ad1dd637d854bc78847 from qemu		2018-03-04 00:20:09 -05:00
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cpu-qom.h
cpu.c
cpu.h	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
dsp_helper.c
helper.c	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
helper.h
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
TODO
translate_init.c	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
translate.c	target/mips: Decode MIPS32 EVA load & store instructions	2018-03-04 00:20:09 -05:00
unicorn.c
unicorn.h