unicorn/qemu/target/riscv
Bastian Koppelmann 28daad082b
target/riscv: Remove manual decoding of RV32/64M insn
Backports commit 1288701682d81b93f62e01cd87001dc90b30b881 from qemu
2019-03-19 05:34:32 -04:00
..
insn_trans target/riscv: Remove manual decoding of RV32/64M insn 2019-03-19 05:34:32 -04:00
cpu_bits.h
cpu_helper.c
cpu_user.h
cpu.c
cpu.h
csr.c
fpu_helper.c
helper.h
insn16.decode target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-19 04:53:07 -04:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
insn32.decode target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 2019-03-19 05:17:54 -04:00
instmap.h
Makefile.objs target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-19 04:45:53 -04:00
op_helper.c
pmp.c
pmp.h
translate.c target/riscv: Remove manual decoding of RV32/64M insn 2019-03-19 05:34:32 -04:00
unicorn.c
unicorn.h