Peter Maydell e07cd2542c exec.c: Drop TARGET_HAS_ICE define and checks ... The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Backports commit ec53b45bcd1f74f7a4c31331fa6d50b402cd6d26 from qemu		2018-02-18 18:17:14 -05:00
..
cc_helper.c	Sparc support added. (#734)	2017-01-23 13:29:41 +08:00
cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	target-sparc: Convert to VMStateDescription	2018-02-17 21:06:46 -05:00
cpu.h	exec.c: Drop TARGET_HAS_ICE define and checks	2018-02-18 18:17:14 -05:00
fop_helper.c
helper.c	do not use syscall to quit emulation. this can fix issues #147 & #148	2015-09-26 16:49:00 +08:00
helper.h	rework code/block tracing	2016-01-22 18:42:27 -08:00
int32_helper.c
int64_helper.c	Sparc support added. (#734)	2017-01-23 13:29:41 +08:00
ldst_helper.c	Sparc support added. (#734)	2017-01-23 13:29:41 +08:00
Makefile.objs	cleanup Sparc unused code	2017-01-23 12:34:00 +08:00
mmu_helper.c	tlb: Add ifetch argument to cpu_mmu_index()	2018-02-17 15:23:37 -05:00
TODO
translate.c	sparc: allow CASA with ASI 0xa from user space	2018-02-17 19:23:35 -05:00
unicorn64.c	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
unicorn.c	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
unicorn.h	New feature: registers can be bulk saved/restored in an opaque blob	2016-08-20 04:14:07 -07:00
vis_helper.c	target-sparc: fix 32-bit truncation in fpackfix	2018-02-17 19:08:40 -05:00
win_helper.c	target-sparc: Split cpu_put_psr into side-effect and no-side-effect parts	2018-02-17 21:04:15 -05:00