Richard Henderson 2a4a7b9391 tcg: Use tlb_fill probe from tlb_vaddr_to_host ... Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for AArch64 SVE we have an existing emulation bug wherein we would mark the first element of a no-fault vector load as faulted (within the FFR, not via exception) just because we did not have its address in the TLB. Now we can properly only mark it as faulted if there really is no valid, readable translation, while still not raising an exception. (Note that beyond the first element of the vector, the hardware may report a fault for any reason whatsoever; with at least one element loaded, forward progress is guaranteed.) Backports commit 4811e9095c0491bc6f5450e5012c9c4796b9e59d from qemu		2019-05-16 18:27:03 -04:00
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atomic_template.h	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
cpu-exec-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
cpu-exec.c	tcg: Remove CF_IGNORE_ICOUNT	2019-05-06 00:57:09 -04:00
cputlb.c	tcg: Use tlb_fill probe from tlb_vaddr_to_host	2019-05-16 18:27:03 -04:00
Makefile.objs	tcg: move tcg backend files into accel/tcg/	2018-03-13 11:48:15 -04:00
tcg-runtime-gvec.c	tcg: Add support for vector absolute value	2019-05-16 16:33:43 -04:00
tcg-runtime.c	tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK	2019-05-04 22:22:06 -04:00
tcg-runtime.h	tcg: Add support for vector absolute value	2019-05-16 16:33:43 -04:00
translate-all.c	tcg: check CF_PARALLEL instead of parallel_cpus	2019-05-06 00:52:08 -04:00
translate-all.h	tcg: Synchronize with qemu	2019-04-26 09:32:20 -04:00
translate-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
translator.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00