Emilio G. Cota 9aaad9ed27 target/arm: optimize indirect branches ... Speed up indirect branches by jumping to the target if it is valid. Softmmu measurements (see later commit for user-mode results): Note: baseline (i.e. speedup == 1x) is QEMU v2.9.0. - Impact on Boot time | setup | ARM debian jessie boot+shutdown time | stddev | |--------+--------------------------------------+--------| | v2.9.0 | 8.84 | 0.07 | | +cross | 8.85 | 0.03 | | +jr | 8.83 | 0.06 | - NBench, arm-softmmu (debian jessie guest). Host: Intel i7-4790K @ 4.00GHz 1.3x +-+-------------------------------------------------------------------------------------------------------------+-+ | | | cross #### | 1.25x +cross+jr..........................................................#++#.........................................+-+ | #### # # | | +++# # # # | | +++ **** # # # | 1.2x +-+...................................####............*..*..#......#..#.........................................+-+ | **** # * * # # # #### | | * * # * * # # # # # | 1.15x +-+................................*..*..#............*..*..#......#..#.....#..#................................+-+ | * * # * * # # # # # | | * * # #### * * # # # # # | | * * # # # * * # # # # # #### | 1.1x +-+................................*..*..#......#..#..*..*..#......#..#.....#..#.........................#..#...+-+ | * * # # # * * # # # # # # # | | * * # # # * * # # # # # # # | 1.05x +-+..........................####..*..*..#......#..#..*..*..#......#..#.....#..#......+++............*****..#...+-+ | ***** # * * # # # * * # ***** # # # +++ | ****### * * # | | *+++* # * * # # # * * # *+++* # **** # *****### * * # * * # | | *****### +++#### * * # * * # ***** # * * # * * # * * # * | *++# * * # * * # | 1x +-++-+*+++*-+#++****++#++*+-+*++#+-*++*++#-+*+++*-+#++*++*++#++*+-+*++#+-*++*++#-+*+++*-+#++*++*++#++*+-+*++#+-++-+ | * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | | * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | 0.95x +-+---*****###--****###--*****###--****###--*****###--****###--*****###--****###--*****###--****###--*****###---+-+ ASSIGNMENT BITFIELD FOURFP EMULATION HUFFMAN LU DECOMPOSITIONEURAL NNUMERIC SOSTRING SORT hmean png: http://imgur.com/eOLmZNR NB. 'cross' represents the previous commit. Backports commit 8a6b28c7b5104263344508df0f4bce97f22cfcaf from qemu		2018-03-02 21:18:15 -05:00
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arm_ldst.h	Fix Thumb-1 BE32 execution and disassembly.	2018-03-02 00:20:11 -05:00
arm-powerctl.c	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
arm-powerctl.h	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
cpu64.c	target-arm: Enable EL2 feature bit on A53 and A57	2018-03-01 23:36:44 -05:00
cpu-qom.h
cpu.c	target/arm: add data cache invalidation cp15 instruction to cortex-r5	2018-03-02 20:04:20 -05:00
cpu.h	armv7m: Check exception return consistency	2018-03-02 19:59:18 -05:00
crypto_helper.c
helper-a64.c
helper-a64.h
helper.c	armv7m: Raise correct kind of UsageFault for attempts to execute ARM code	2018-03-02 20:00:58 -05:00
helper.h
internals.h	arm: Move excnames[] array into arm_log_exceptions()	2018-03-02 14:39:37 -05:00
iwmmxt_helper.c
kvm-consts.h	arm: better stub version for MISMATCH_CHECK	2018-03-02 00:13:45 -05:00
Makefile.objs	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
neon_helper.c
op_addsub.h
op_helper.c	arm: Add support for M profile CPUs having different MMU index semantics	2018-03-02 18:59:13 -05:00
psci.c	target/arm/psci.c: If EL2 implemented, start CPUs in EL2	2018-03-01 23:34:57 -05:00
translate-a64.c	arm: Add support for M profile CPUs having different MMU index semantics	2018-03-02 18:59:13 -05:00
translate.c	target/arm: optimize indirect branches	2018-03-02 21:18:15 -05:00
translate.h	target/arm: optimize indirect branches	2018-03-02 21:18:15 -05:00
unicorn_aarch64.c
unicorn_arm.c
unicorn.h