Aleksandar Markovic 3a276522ac target/mips: Amend preprocessor constants for CP0 registers ... Correct existing CP0-related preprocessor constants (replace "CPO" with "CP0" (form letter "O" to digit "0", when needed). Besides, add preprocessor constants for CP0 subregisters. The names of the subregisters were chosen to be in sync with the table of corresponding assembler mnemonics found in the documentation for I6500 and I6400 (release 1.0). Backports commit 04992c8cd1c43ecdba39dd8c916db092db6ebae0 from qemu		2019-01-22 19:55:04 -05:00
..
accel	tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE	2018-11-16 21:35:54 -05:00
crypto
default-configs
docs
fpu	hardfloat: implement float32/64 comparison	2018-12-19 10:45:22 -05:00
hw
include	qemu/compiler: Add fallback macro for __has_builtin	2019-01-22 19:02:49 -05:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qobject
qom
scripts	qapi: fix flat union on uncovered branches conditionals	2018-12-19 10:53:29 -05:00
target	target/mips: Amend preprocessor constants for CP0 registers	2019-01-22 19:55:04 -05:00
tcg	tcg: Improve call argument loading	2019-01-05 07:24:08 -05:00
util	qemu-thread: Don't block SEGV, ILL and FPE	2019-01-13 19:50:32 -05:00
aarch64.h	target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0	2019-01-22 17:45:36 -05:00
aarch64eb.h	target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0	2019-01-22 17:45:36 -05:00
accel.c
arm.h	target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0	2019-01-22 17:45:36 -05:00
armeb.h	target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0	2019-01-22 17:45:36 -05:00
CODING_STYLE
configure	configure: keep track of Python version	2019-01-22 15:07:59 -05:00
COPYING
COPYING.LIB
cpus.c
exec.c	Partial backport of: exec.c: Handle IOMMUs in address_space_translate_for_iotlb()	2018-11-16 21:24:55 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
ioport.c
LICENSE
m68k.h	target/arm: Reorganize PMCCNTR accesses	2019-01-22 16:57:29 -05:00
Makefile
Makefile.objs
Makefile.target	configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012]	2018-12-18 03:52:36 -05:00
memory_ldst.inc.c
memory_mapping.c
memory.c	memory: learn about non-volatile memory region	2018-11-11 08:50:39 -05:00
mips64.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
mips64el.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
mips.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
mipsel.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
powerpc.h	target/arm: Reorganize PMCCNTR accesses	2019-01-22 16:57:29 -05:00
qemu-timer.c
riscv32.h
riscv64.h
rules.mak
sparc64.h	target/arm: Reorganize PMCCNTR accesses	2019-01-22 16:57:29 -05:00
sparc.h	target/arm: Reorganize PMCCNTR accesses	2019-01-22 16:57:29 -05:00
unicorn_common.h
VERSION	Open 4.0 development tree	2018-12-11 20:33:45 -05:00
vl.c
vl.h
x86_64.h	target/arm: Reorganize PMCCNTR accesses	2019-01-22 16:57:29 -05:00