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default-configs
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docs
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docs: clarify memory region lifecycle
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2018-02-12 15:11:21 -05:00 |
fpu
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softfloat: expand out STATUS macro
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2018-02-12 13:43:13 -05:00 |
hw
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target-i386: disable LINT0 after reset
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2018-02-12 21:07:36 -05:00 |
include
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target-i386: introduce cpu_get_mem_attrs
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2018-02-13 11:33:39 -05:00 |
qapi
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qobject
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qom
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qom: Fix object_property_add_alias() with [*]
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2018-02-12 16:33:58 -05:00 |
scripts
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target-arm
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unicorn_arm: m68k/translate: Build fixes
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2018-02-13 09:15:46 -05:00 |
target-i386
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target-i386: create a separate AddressSpace for each CPU
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2018-02-13 12:36:26 -05:00 |
target-m68k
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unicorn_arm: m68k/translate: Build fixes
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2018-02-13 09:15:46 -05:00 |
target-mips
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target-mips: enable XPA and LPA features
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2018-02-13 14:14:59 -05:00 |
target-sparc
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target-*: Increment num_insns immediately after tcg_gen_insn_start
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2018-02-11 12:46:30 -05:00 |
tcg
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tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
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2018-02-13 08:28:29 -05:00 |
util
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bitmap: add atomic test and clear
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2018-02-13 10:02:12 -05:00 |
aarch64.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
aarch64eb.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
accel.c
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arm.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
armeb.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
CODING_STYLE
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configure
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COPYING
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COPYING.LIB
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cpu-exec.c
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exec: make iotlb RCU-friendly
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2018-02-12 15:20:39 -05:00 |
cpus.c
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cleanup more synchronization code
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2017-01-09 14:05:39 +08:00 |
cputlb.c
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memory: replace cpu_physical_memory_reset_dirty() with test-and-clear
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2018-02-13 11:25:45 -05:00 |
exec.c
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memory: replace cpu_physical_memory_reset_dirty() with test-and-clear
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2018-02-13 11:25:45 -05:00 |
gen_all_header.sh
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glib_compat.c
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HACKING
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header_gen.py
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target-mips: add ERETNC instruction and Config5.LLB bit
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2018-02-13 13:33:37 -05:00 |
ioport.c
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memory: Define API for MemoryRegionOps to take attrs and return status
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2018-02-12 17:17:27 -05:00 |
LICENSE
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m68k.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
Makefile
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Makefile.objs
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Makefile.target
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memory_mapping.c
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memory.c
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memory: use mr->ram_addr in "is this RAM?" assertions
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2018-02-13 11:31:02 -05:00 |
mips64.h
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target-mips: add ERETNC instruction and Config5.LLB bit
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2018-02-13 13:33:37 -05:00 |
mips64el.h
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target-mips: add ERETNC instruction and Config5.LLB bit
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2018-02-13 13:33:37 -05:00 |
mips.h
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target-mips: add ERETNC instruction and Config5.LLB bit
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2018-02-13 13:33:37 -05:00 |
mipsel.h
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target-mips: add ERETNC instruction and Config5.LLB bit
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2018-02-13 13:33:37 -05:00 |
powerpc.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
qapi-schema.json
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qemu-log.c
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qemu-timer.c
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rules.mak
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softmmu_template.h
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Add MemTxAttrs to the IOTLB
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2018-02-12 18:38:38 -05:00 |
sparc64.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
sparc.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |
tcg-runtime.c
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platform.h move #3
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2017-01-21 00:13:21 +11:00 |
translate-all.c
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translate-all: make less of tb_invalidate_phys_page_range depend on is_cpu_write_access
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2018-02-13 09:18:49 -05:00 |
translate-all.h
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translate-all: remove unnecessary argument to tb_invalidate_phys_range
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2018-02-13 09:04:51 -05:00 |
unicorn_common.h
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VERSION
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vl.c
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This code should now build the x86_x64-softmmu part 2.
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2017-01-19 22:50:28 +11:00 |
vl.h
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x86_64.h
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target-mips: Misaligned memory accesses for MSA
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2018-02-13 13:27:31 -05:00 |