Richard Henderson 2a4a7b9391 tcg: Use tlb_fill probe from tlb_vaddr_to_host ... Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for AArch64 SVE we have an existing emulation bug wherein we would mark the first element of a no-fault vector load as faulted (within the FFR, not via exception) just because we did not have its address in the TLB. Now we can properly only mark it as faulted if there really is no valid, readable translation, while still not raising an exception. (Note that beyond the first element of the vector, the hardware may report a fault for any reason whatsoever; with at least one element loaded, forward progress is guaranteed.) Backports commit 4811e9095c0491bc6f5450e5012c9c4796b9e59d from qemu		2019-05-16 18:27:03 -04:00
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crypto
exec	tcg: Use tlb_fill probe from tlb_vaddr_to_host	2019-05-16 18:27:03 -04:00
fpu	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qemu	osdep: Fix mingw compilation regarding stdio formats	2019-05-09 17:44:14 -04:00
qom	tcg: Remove CPUClass::handle_mmu_fault	2019-05-16 18:12:17 -04:00
sysemu	accel: Remove unused AccelClass::available field	2019-05-03 11:31:27 -04:00
config.h
elf.h
glib_compat.h	target/arm/translate: Synchronize with Qemu	2019-04-27 10:13:01 -04:00
qemu-common.h